1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MESON_CLK_PLL_H 8*4882a593Smuzhiyun #define __MESON_CLK_PLL_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/clk-provider.h> 11*4882a593Smuzhiyun #include <linux/regmap.h> 12*4882a593Smuzhiyun #include "parm.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct pll_params_table { 15*4882a593Smuzhiyun unsigned int m; 16*4882a593Smuzhiyun unsigned int n; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct pll_mult_range { 20*4882a593Smuzhiyun unsigned int min; 21*4882a593Smuzhiyun unsigned int max; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PLL_PARAMS(_m, _n) \ 25*4882a593Smuzhiyun { \ 26*4882a593Smuzhiyun .m = (_m), \ 27*4882a593Smuzhiyun .n = (_n), \ 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct meson_clk_pll_data { 33*4882a593Smuzhiyun struct parm en; 34*4882a593Smuzhiyun struct parm m; 35*4882a593Smuzhiyun struct parm n; 36*4882a593Smuzhiyun struct parm frac; 37*4882a593Smuzhiyun struct parm l; 38*4882a593Smuzhiyun struct parm rst; 39*4882a593Smuzhiyun const struct reg_sequence *init_regs; 40*4882a593Smuzhiyun unsigned int init_count; 41*4882a593Smuzhiyun const struct pll_params_table *table; 42*4882a593Smuzhiyun const struct pll_mult_range *range; 43*4882a593Smuzhiyun u8 flags; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern const struct clk_ops meson_clk_pll_ro_ops; 47*4882a593Smuzhiyun extern const struct clk_ops meson_clk_pll_ops; 48*4882a593Smuzhiyun extern const struct clk_ops meson_clk_pcie_pll_ops; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* __MESON_CLK_PLL_H */ 51