1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS.
4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-regmap.h"
11*4882a593Smuzhiyun #include "clk-cpu-dyndiv.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static inline struct meson_clk_cpu_dyndiv_data *
meson_clk_cpu_dyndiv_data(struct clk_regmap * clk)14*4882a593Smuzhiyun meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun return (struct meson_clk_cpu_dyndiv_data *)clk->data;
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw * hw,unsigned long prate)19*4882a593Smuzhiyun static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
20*4882a593Smuzhiyun unsigned long prate)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun struct clk_regmap *clk = to_clk_regmap(hw);
23*4882a593Smuzhiyun struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun return divider_recalc_rate(hw, prate,
26*4882a593Smuzhiyun meson_parm_read(clk->map, &data->div),
27*4882a593Smuzhiyun NULL, 0, data->div.width);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
meson_clk_cpu_dyndiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)30*4882a593Smuzhiyun static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
31*4882a593Smuzhiyun unsigned long rate,
32*4882a593Smuzhiyun unsigned long *prate)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct clk_regmap *clk = to_clk_regmap(hw);
35*4882a593Smuzhiyun struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
meson_clk_cpu_dyndiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)40*4882a593Smuzhiyun static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
41*4882a593Smuzhiyun unsigned long parent_rate)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct clk_regmap *clk = to_clk_regmap(hw);
44*4882a593Smuzhiyun struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
45*4882a593Smuzhiyun unsigned int val;
46*4882a593Smuzhiyun int ret;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
49*4882a593Smuzhiyun if (ret < 0)
50*4882a593Smuzhiyun return ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun val = (unsigned int)ret << data->div.shift;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
55*4882a593Smuzhiyun meson_parm_write(clk->map, &data->dyn, 1);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
58*4882a593Smuzhiyun return regmap_update_bits(clk->map, data->div.reg_off,
59*4882a593Smuzhiyun SETPMASK(data->div.width, data->div.shift) |
60*4882a593Smuzhiyun SETPMASK(data->dyn.width, data->dyn.shift),
61*4882a593Smuzhiyun val);
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun const struct clk_ops meson_clk_cpu_dyndiv_ops = {
65*4882a593Smuzhiyun .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
66*4882a593Smuzhiyun .round_rate = meson_clk_cpu_dyndiv_round_rate,
67*4882a593Smuzhiyun .set_rate = meson_clk_cpu_dyndiv_set_rate,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
72*4882a593Smuzhiyun MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
73*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
74