1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/module.h> 17 18 #include "clk-regmap.h" 19 #include "clk-pll.h" 20 #include "clk-mpll.h" 21 #include "axg.h" 22 #include "meson-eeclk.h" 23 24 static DEFINE_SPINLOCK(meson_clk_lock); 25 26 static struct clk_regmap axg_fixed_pll_dco = { 27 .data = &(struct meson_clk_pll_data){ 28 .en = { 29 .reg_off = HHI_MPLL_CNTL, 30 .shift = 30, 31 .width = 1, 32 }, 33 .m = { 34 .reg_off = HHI_MPLL_CNTL, 35 .shift = 0, 36 .width = 9, 37 }, 38 .n = { 39 .reg_off = HHI_MPLL_CNTL, 40 .shift = 9, 41 .width = 5, 42 }, 43 .frac = { 44 .reg_off = HHI_MPLL_CNTL2, 45 .shift = 0, 46 .width = 12, 47 }, 48 .l = { 49 .reg_off = HHI_MPLL_CNTL, 50 .shift = 31, 51 .width = 1, 52 }, 53 .rst = { 54 .reg_off = HHI_MPLL_CNTL, 55 .shift = 29, 56 .width = 1, 57 }, 58 }, 59 .hw.init = &(struct clk_init_data){ 60 .name = "fixed_pll_dco", 61 .ops = &meson_clk_pll_ro_ops, 62 .parent_data = &(const struct clk_parent_data) { 63 .fw_name = "xtal", 64 }, 65 .num_parents = 1, 66 }, 67 }; 68 69 static struct clk_regmap axg_fixed_pll = { 70 .data = &(struct clk_regmap_div_data){ 71 .offset = HHI_MPLL_CNTL, 72 .shift = 16, 73 .width = 2, 74 .flags = CLK_DIVIDER_POWER_OF_TWO, 75 }, 76 .hw.init = &(struct clk_init_data){ 77 .name = "fixed_pll", 78 .ops = &clk_regmap_divider_ro_ops, 79 .parent_hws = (const struct clk_hw *[]) { 80 &axg_fixed_pll_dco.hw 81 }, 82 .num_parents = 1, 83 /* 84 * This clock won't ever change at runtime so 85 * CLK_SET_RATE_PARENT is not required 86 */ 87 }, 88 }; 89 90 static struct clk_regmap axg_sys_pll_dco = { 91 .data = &(struct meson_clk_pll_data){ 92 .en = { 93 .reg_off = HHI_SYS_PLL_CNTL, 94 .shift = 30, 95 .width = 1, 96 }, 97 .m = { 98 .reg_off = HHI_SYS_PLL_CNTL, 99 .shift = 0, 100 .width = 9, 101 }, 102 .n = { 103 .reg_off = HHI_SYS_PLL_CNTL, 104 .shift = 9, 105 .width = 5, 106 }, 107 .l = { 108 .reg_off = HHI_SYS_PLL_CNTL, 109 .shift = 31, 110 .width = 1, 111 }, 112 .rst = { 113 .reg_off = HHI_SYS_PLL_CNTL, 114 .shift = 29, 115 .width = 1, 116 }, 117 }, 118 .hw.init = &(struct clk_init_data){ 119 .name = "sys_pll_dco", 120 .ops = &meson_clk_pll_ro_ops, 121 .parent_data = &(const struct clk_parent_data) { 122 .fw_name = "xtal", 123 }, 124 .num_parents = 1, 125 }, 126 }; 127 128 static struct clk_regmap axg_sys_pll = { 129 .data = &(struct clk_regmap_div_data){ 130 .offset = HHI_SYS_PLL_CNTL, 131 .shift = 16, 132 .width = 2, 133 .flags = CLK_DIVIDER_POWER_OF_TWO, 134 }, 135 .hw.init = &(struct clk_init_data){ 136 .name = "sys_pll", 137 .ops = &clk_regmap_divider_ro_ops, 138 .parent_hws = (const struct clk_hw *[]) { 139 &axg_sys_pll_dco.hw 140 }, 141 .num_parents = 1, 142 .flags = CLK_SET_RATE_PARENT, 143 }, 144 }; 145 146 static const struct pll_params_table axg_gp0_pll_params_table[] = { 147 PLL_PARAMS(40, 1), 148 PLL_PARAMS(41, 1), 149 PLL_PARAMS(42, 1), 150 PLL_PARAMS(43, 1), 151 PLL_PARAMS(44, 1), 152 PLL_PARAMS(45, 1), 153 PLL_PARAMS(46, 1), 154 PLL_PARAMS(47, 1), 155 PLL_PARAMS(48, 1), 156 PLL_PARAMS(49, 1), 157 PLL_PARAMS(50, 1), 158 PLL_PARAMS(51, 1), 159 PLL_PARAMS(52, 1), 160 PLL_PARAMS(53, 1), 161 PLL_PARAMS(54, 1), 162 PLL_PARAMS(55, 1), 163 PLL_PARAMS(56, 1), 164 PLL_PARAMS(57, 1), 165 PLL_PARAMS(58, 1), 166 PLL_PARAMS(59, 1), 167 PLL_PARAMS(60, 1), 168 PLL_PARAMS(61, 1), 169 PLL_PARAMS(62, 1), 170 PLL_PARAMS(63, 1), 171 PLL_PARAMS(64, 1), 172 PLL_PARAMS(65, 1), 173 PLL_PARAMS(66, 1), 174 PLL_PARAMS(67, 1), 175 PLL_PARAMS(68, 1), 176 { /* sentinel */ }, 177 }; 178 179 static const struct reg_sequence axg_gp0_init_regs[] = { 180 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 181 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 182 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 183 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 184 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 185 }; 186 187 static struct clk_regmap axg_gp0_pll_dco = { 188 .data = &(struct meson_clk_pll_data){ 189 .en = { 190 .reg_off = HHI_GP0_PLL_CNTL, 191 .shift = 30, 192 .width = 1, 193 }, 194 .m = { 195 .reg_off = HHI_GP0_PLL_CNTL, 196 .shift = 0, 197 .width = 9, 198 }, 199 .n = { 200 .reg_off = HHI_GP0_PLL_CNTL, 201 .shift = 9, 202 .width = 5, 203 }, 204 .frac = { 205 .reg_off = HHI_GP0_PLL_CNTL1, 206 .shift = 0, 207 .width = 10, 208 }, 209 .l = { 210 .reg_off = HHI_GP0_PLL_CNTL, 211 .shift = 31, 212 .width = 1, 213 }, 214 .rst = { 215 .reg_off = HHI_GP0_PLL_CNTL, 216 .shift = 29, 217 .width = 1, 218 }, 219 .table = axg_gp0_pll_params_table, 220 .init_regs = axg_gp0_init_regs, 221 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 222 }, 223 .hw.init = &(struct clk_init_data){ 224 .name = "gp0_pll_dco", 225 .ops = &meson_clk_pll_ops, 226 .parent_data = &(const struct clk_parent_data) { 227 .fw_name = "xtal", 228 }, 229 .num_parents = 1, 230 }, 231 }; 232 233 static struct clk_regmap axg_gp0_pll = { 234 .data = &(struct clk_regmap_div_data){ 235 .offset = HHI_GP0_PLL_CNTL, 236 .shift = 16, 237 .width = 2, 238 .flags = CLK_DIVIDER_POWER_OF_TWO, 239 }, 240 .hw.init = &(struct clk_init_data){ 241 .name = "gp0_pll", 242 .ops = &clk_regmap_divider_ops, 243 .parent_hws = (const struct clk_hw *[]) { 244 &axg_gp0_pll_dco.hw 245 }, 246 .num_parents = 1, 247 .flags = CLK_SET_RATE_PARENT, 248 }, 249 }; 250 251 static const struct reg_sequence axg_hifi_init_regs[] = { 252 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 253 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 254 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 255 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 256 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 257 }; 258 259 static struct clk_regmap axg_hifi_pll_dco = { 260 .data = &(struct meson_clk_pll_data){ 261 .en = { 262 .reg_off = HHI_HIFI_PLL_CNTL, 263 .shift = 30, 264 .width = 1, 265 }, 266 .m = { 267 .reg_off = HHI_HIFI_PLL_CNTL, 268 .shift = 0, 269 .width = 9, 270 }, 271 .n = { 272 .reg_off = HHI_HIFI_PLL_CNTL, 273 .shift = 9, 274 .width = 5, 275 }, 276 .frac = { 277 .reg_off = HHI_HIFI_PLL_CNTL5, 278 .shift = 0, 279 .width = 13, 280 }, 281 .l = { 282 .reg_off = HHI_HIFI_PLL_CNTL, 283 .shift = 31, 284 .width = 1, 285 }, 286 .rst = { 287 .reg_off = HHI_HIFI_PLL_CNTL, 288 .shift = 29, 289 .width = 1, 290 }, 291 .table = axg_gp0_pll_params_table, 292 .init_regs = axg_hifi_init_regs, 293 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 294 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 295 }, 296 .hw.init = &(struct clk_init_data){ 297 .name = "hifi_pll_dco", 298 .ops = &meson_clk_pll_ops, 299 .parent_data = &(const struct clk_parent_data) { 300 .fw_name = "xtal", 301 }, 302 .num_parents = 1, 303 }, 304 }; 305 306 static struct clk_regmap axg_hifi_pll = { 307 .data = &(struct clk_regmap_div_data){ 308 .offset = HHI_HIFI_PLL_CNTL, 309 .shift = 16, 310 .width = 2, 311 .flags = CLK_DIVIDER_POWER_OF_TWO, 312 }, 313 .hw.init = &(struct clk_init_data){ 314 .name = "hifi_pll", 315 .ops = &clk_regmap_divider_ops, 316 .parent_hws = (const struct clk_hw *[]) { 317 &axg_hifi_pll_dco.hw 318 }, 319 .num_parents = 1, 320 .flags = CLK_SET_RATE_PARENT, 321 }, 322 }; 323 324 static struct clk_fixed_factor axg_fclk_div2_div = { 325 .mult = 1, 326 .div = 2, 327 .hw.init = &(struct clk_init_data){ 328 .name = "fclk_div2_div", 329 .ops = &clk_fixed_factor_ops, 330 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 331 .num_parents = 1, 332 }, 333 }; 334 335 static struct clk_regmap axg_fclk_div2 = { 336 .data = &(struct clk_regmap_gate_data){ 337 .offset = HHI_MPLL_CNTL6, 338 .bit_idx = 27, 339 }, 340 .hw.init = &(struct clk_init_data){ 341 .name = "fclk_div2", 342 .ops = &clk_regmap_gate_ops, 343 .parent_hws = (const struct clk_hw *[]) { 344 &axg_fclk_div2_div.hw 345 }, 346 .num_parents = 1, 347 .flags = CLK_IS_CRITICAL, 348 }, 349 }; 350 351 static struct clk_fixed_factor axg_fclk_div3_div = { 352 .mult = 1, 353 .div = 3, 354 .hw.init = &(struct clk_init_data){ 355 .name = "fclk_div3_div", 356 .ops = &clk_fixed_factor_ops, 357 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 358 .num_parents = 1, 359 }, 360 }; 361 362 static struct clk_regmap axg_fclk_div3 = { 363 .data = &(struct clk_regmap_gate_data){ 364 .offset = HHI_MPLL_CNTL6, 365 .bit_idx = 28, 366 }, 367 .hw.init = &(struct clk_init_data){ 368 .name = "fclk_div3", 369 .ops = &clk_regmap_gate_ops, 370 .parent_hws = (const struct clk_hw *[]) { 371 &axg_fclk_div3_div.hw 372 }, 373 .num_parents = 1, 374 /* 375 * FIXME: 376 * This clock, as fdiv2, is used by the SCPI FW and is required 377 * by the platform to operate correctly. 378 * Until the following condition are met, we need this clock to 379 * be marked as critical: 380 * a) The SCPI generic driver claims and enable all the clocks 381 * it needs 382 * b) CCF has a clock hand-off mechanism to make the sure the 383 * clock stays on until the proper driver comes along 384 */ 385 .flags = CLK_IS_CRITICAL, 386 }, 387 }; 388 389 static struct clk_fixed_factor axg_fclk_div4_div = { 390 .mult = 1, 391 .div = 4, 392 .hw.init = &(struct clk_init_data){ 393 .name = "fclk_div4_div", 394 .ops = &clk_fixed_factor_ops, 395 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 396 .num_parents = 1, 397 }, 398 }; 399 400 static struct clk_regmap axg_fclk_div4 = { 401 .data = &(struct clk_regmap_gate_data){ 402 .offset = HHI_MPLL_CNTL6, 403 .bit_idx = 29, 404 }, 405 .hw.init = &(struct clk_init_data){ 406 .name = "fclk_div4", 407 .ops = &clk_regmap_gate_ops, 408 .parent_hws = (const struct clk_hw *[]) { 409 &axg_fclk_div4_div.hw 410 }, 411 .num_parents = 1, 412 }, 413 }; 414 415 static struct clk_fixed_factor axg_fclk_div5_div = { 416 .mult = 1, 417 .div = 5, 418 .hw.init = &(struct clk_init_data){ 419 .name = "fclk_div5_div", 420 .ops = &clk_fixed_factor_ops, 421 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 422 .num_parents = 1, 423 }, 424 }; 425 426 static struct clk_regmap axg_fclk_div5 = { 427 .data = &(struct clk_regmap_gate_data){ 428 .offset = HHI_MPLL_CNTL6, 429 .bit_idx = 30, 430 }, 431 .hw.init = &(struct clk_init_data){ 432 .name = "fclk_div5", 433 .ops = &clk_regmap_gate_ops, 434 .parent_hws = (const struct clk_hw *[]) { 435 &axg_fclk_div5_div.hw 436 }, 437 .num_parents = 1, 438 }, 439 }; 440 441 static struct clk_fixed_factor axg_fclk_div7_div = { 442 .mult = 1, 443 .div = 7, 444 .hw.init = &(struct clk_init_data){ 445 .name = "fclk_div7_div", 446 .ops = &clk_fixed_factor_ops, 447 .parent_hws = (const struct clk_hw *[]) { 448 &axg_fixed_pll.hw 449 }, 450 .num_parents = 1, 451 }, 452 }; 453 454 static struct clk_regmap axg_fclk_div7 = { 455 .data = &(struct clk_regmap_gate_data){ 456 .offset = HHI_MPLL_CNTL6, 457 .bit_idx = 31, 458 }, 459 .hw.init = &(struct clk_init_data){ 460 .name = "fclk_div7", 461 .ops = &clk_regmap_gate_ops, 462 .parent_hws = (const struct clk_hw *[]) { 463 &axg_fclk_div7_div.hw 464 }, 465 .num_parents = 1, 466 }, 467 }; 468 469 static struct clk_regmap axg_mpll_prediv = { 470 .data = &(struct clk_regmap_div_data){ 471 .offset = HHI_MPLL_CNTL5, 472 .shift = 12, 473 .width = 1, 474 }, 475 .hw.init = &(struct clk_init_data){ 476 .name = "mpll_prediv", 477 .ops = &clk_regmap_divider_ro_ops, 478 .parent_hws = (const struct clk_hw *[]) { 479 &axg_fixed_pll.hw 480 }, 481 .num_parents = 1, 482 }, 483 }; 484 485 static struct clk_regmap axg_mpll0_div = { 486 .data = &(struct meson_clk_mpll_data){ 487 .sdm = { 488 .reg_off = HHI_MPLL_CNTL7, 489 .shift = 0, 490 .width = 14, 491 }, 492 .sdm_en = { 493 .reg_off = HHI_MPLL_CNTL7, 494 .shift = 15, 495 .width = 1, 496 }, 497 .n2 = { 498 .reg_off = HHI_MPLL_CNTL7, 499 .shift = 16, 500 .width = 9, 501 }, 502 .misc = { 503 .reg_off = HHI_PLL_TOP_MISC, 504 .shift = 0, 505 .width = 1, 506 }, 507 .lock = &meson_clk_lock, 508 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 509 }, 510 .hw.init = &(struct clk_init_data){ 511 .name = "mpll0_div", 512 .ops = &meson_clk_mpll_ops, 513 .parent_hws = (const struct clk_hw *[]) { 514 &axg_mpll_prediv.hw 515 }, 516 .num_parents = 1, 517 }, 518 }; 519 520 static struct clk_regmap axg_mpll0 = { 521 .data = &(struct clk_regmap_gate_data){ 522 .offset = HHI_MPLL_CNTL7, 523 .bit_idx = 14, 524 }, 525 .hw.init = &(struct clk_init_data){ 526 .name = "mpll0", 527 .ops = &clk_regmap_gate_ops, 528 .parent_hws = (const struct clk_hw *[]) { 529 &axg_mpll0_div.hw 530 }, 531 .num_parents = 1, 532 .flags = CLK_SET_RATE_PARENT, 533 }, 534 }; 535 536 static struct clk_regmap axg_mpll1_div = { 537 .data = &(struct meson_clk_mpll_data){ 538 .sdm = { 539 .reg_off = HHI_MPLL_CNTL8, 540 .shift = 0, 541 .width = 14, 542 }, 543 .sdm_en = { 544 .reg_off = HHI_MPLL_CNTL8, 545 .shift = 15, 546 .width = 1, 547 }, 548 .n2 = { 549 .reg_off = HHI_MPLL_CNTL8, 550 .shift = 16, 551 .width = 9, 552 }, 553 .misc = { 554 .reg_off = HHI_PLL_TOP_MISC, 555 .shift = 1, 556 .width = 1, 557 }, 558 .lock = &meson_clk_lock, 559 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 560 }, 561 .hw.init = &(struct clk_init_data){ 562 .name = "mpll1_div", 563 .ops = &meson_clk_mpll_ops, 564 .parent_hws = (const struct clk_hw *[]) { 565 &axg_mpll_prediv.hw 566 }, 567 .num_parents = 1, 568 }, 569 }; 570 571 static struct clk_regmap axg_mpll1 = { 572 .data = &(struct clk_regmap_gate_data){ 573 .offset = HHI_MPLL_CNTL8, 574 .bit_idx = 14, 575 }, 576 .hw.init = &(struct clk_init_data){ 577 .name = "mpll1", 578 .ops = &clk_regmap_gate_ops, 579 .parent_hws = (const struct clk_hw *[]) { 580 &axg_mpll1_div.hw 581 }, 582 .num_parents = 1, 583 .flags = CLK_SET_RATE_PARENT, 584 }, 585 }; 586 587 static struct clk_regmap axg_mpll2_div = { 588 .data = &(struct meson_clk_mpll_data){ 589 .sdm = { 590 .reg_off = HHI_MPLL_CNTL9, 591 .shift = 0, 592 .width = 14, 593 }, 594 .sdm_en = { 595 .reg_off = HHI_MPLL_CNTL9, 596 .shift = 15, 597 .width = 1, 598 }, 599 .n2 = { 600 .reg_off = HHI_MPLL_CNTL9, 601 .shift = 16, 602 .width = 9, 603 }, 604 .ssen = { 605 .reg_off = HHI_MPLL_CNTL, 606 .shift = 25, 607 .width = 1, 608 }, 609 .misc = { 610 .reg_off = HHI_PLL_TOP_MISC, 611 .shift = 2, 612 .width = 1, 613 }, 614 .lock = &meson_clk_lock, 615 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 616 }, 617 .hw.init = &(struct clk_init_data){ 618 .name = "mpll2_div", 619 .ops = &meson_clk_mpll_ops, 620 .parent_hws = (const struct clk_hw *[]) { 621 &axg_mpll_prediv.hw 622 }, 623 .num_parents = 1, 624 }, 625 }; 626 627 static struct clk_regmap axg_mpll2 = { 628 .data = &(struct clk_regmap_gate_data){ 629 .offset = HHI_MPLL_CNTL9, 630 .bit_idx = 14, 631 }, 632 .hw.init = &(struct clk_init_data){ 633 .name = "mpll2", 634 .ops = &clk_regmap_gate_ops, 635 .parent_hws = (const struct clk_hw *[]) { 636 &axg_mpll2_div.hw 637 }, 638 .num_parents = 1, 639 .flags = CLK_SET_RATE_PARENT, 640 }, 641 }; 642 643 static struct clk_regmap axg_mpll3_div = { 644 .data = &(struct meson_clk_mpll_data){ 645 .sdm = { 646 .reg_off = HHI_MPLL3_CNTL0, 647 .shift = 12, 648 .width = 14, 649 }, 650 .sdm_en = { 651 .reg_off = HHI_MPLL3_CNTL0, 652 .shift = 11, 653 .width = 1, 654 }, 655 .n2 = { 656 .reg_off = HHI_MPLL3_CNTL0, 657 .shift = 2, 658 .width = 9, 659 }, 660 .misc = { 661 .reg_off = HHI_PLL_TOP_MISC, 662 .shift = 3, 663 .width = 1, 664 }, 665 .lock = &meson_clk_lock, 666 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 667 }, 668 .hw.init = &(struct clk_init_data){ 669 .name = "mpll3_div", 670 .ops = &meson_clk_mpll_ops, 671 .parent_hws = (const struct clk_hw *[]) { 672 &axg_mpll_prediv.hw 673 }, 674 .num_parents = 1, 675 }, 676 }; 677 678 static struct clk_regmap axg_mpll3 = { 679 .data = &(struct clk_regmap_gate_data){ 680 .offset = HHI_MPLL3_CNTL0, 681 .bit_idx = 0, 682 }, 683 .hw.init = &(struct clk_init_data){ 684 .name = "mpll3", 685 .ops = &clk_regmap_gate_ops, 686 .parent_hws = (const struct clk_hw *[]) { 687 &axg_mpll3_div.hw 688 }, 689 .num_parents = 1, 690 .flags = CLK_SET_RATE_PARENT, 691 }, 692 }; 693 694 static const struct pll_params_table axg_pcie_pll_params_table[] = { 695 { 696 .m = 200, 697 .n = 3, 698 }, 699 { /* sentinel */ }, 700 }; 701 702 static const struct reg_sequence axg_pcie_init_regs[] = { 703 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 704 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 705 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 706 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 707 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 708 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 709 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 710 }; 711 712 static struct clk_regmap axg_pcie_pll_dco = { 713 .data = &(struct meson_clk_pll_data){ 714 .en = { 715 .reg_off = HHI_PCIE_PLL_CNTL, 716 .shift = 30, 717 .width = 1, 718 }, 719 .m = { 720 .reg_off = HHI_PCIE_PLL_CNTL, 721 .shift = 0, 722 .width = 9, 723 }, 724 .n = { 725 .reg_off = HHI_PCIE_PLL_CNTL, 726 .shift = 9, 727 .width = 5, 728 }, 729 .frac = { 730 .reg_off = HHI_PCIE_PLL_CNTL1, 731 .shift = 0, 732 .width = 12, 733 }, 734 .l = { 735 .reg_off = HHI_PCIE_PLL_CNTL, 736 .shift = 31, 737 .width = 1, 738 }, 739 .rst = { 740 .reg_off = HHI_PCIE_PLL_CNTL, 741 .shift = 29, 742 .width = 1, 743 }, 744 .table = axg_pcie_pll_params_table, 745 .init_regs = axg_pcie_init_regs, 746 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 747 }, 748 .hw.init = &(struct clk_init_data){ 749 .name = "pcie_pll_dco", 750 .ops = &meson_clk_pll_ops, 751 .parent_data = &(const struct clk_parent_data) { 752 .fw_name = "xtal", 753 }, 754 .num_parents = 1, 755 }, 756 }; 757 758 static struct clk_regmap axg_pcie_pll_od = { 759 .data = &(struct clk_regmap_div_data){ 760 .offset = HHI_PCIE_PLL_CNTL, 761 .shift = 16, 762 .width = 2, 763 .flags = CLK_DIVIDER_POWER_OF_TWO, 764 }, 765 .hw.init = &(struct clk_init_data){ 766 .name = "pcie_pll_od", 767 .ops = &clk_regmap_divider_ops, 768 .parent_hws = (const struct clk_hw *[]) { 769 &axg_pcie_pll_dco.hw 770 }, 771 .num_parents = 1, 772 .flags = CLK_SET_RATE_PARENT, 773 }, 774 }; 775 776 static struct clk_regmap axg_pcie_pll = { 777 .data = &(struct clk_regmap_div_data){ 778 .offset = HHI_PCIE_PLL_CNTL6, 779 .shift = 6, 780 .width = 2, 781 .flags = CLK_DIVIDER_POWER_OF_TWO, 782 }, 783 .hw.init = &(struct clk_init_data){ 784 .name = "pcie_pll", 785 .ops = &clk_regmap_divider_ops, 786 .parent_hws = (const struct clk_hw *[]) { 787 &axg_pcie_pll_od.hw 788 }, 789 .num_parents = 1, 790 .flags = CLK_SET_RATE_PARENT, 791 }, 792 }; 793 794 static struct clk_regmap axg_pcie_mux = { 795 .data = &(struct clk_regmap_mux_data){ 796 .offset = HHI_PCIE_PLL_CNTL6, 797 .mask = 0x1, 798 .shift = 2, 799 /* skip the parent mpll3, reserved for debug */ 800 .table = (u32[]){ 1 }, 801 }, 802 .hw.init = &(struct clk_init_data){ 803 .name = "pcie_mux", 804 .ops = &clk_regmap_mux_ops, 805 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, 806 .num_parents = 1, 807 .flags = CLK_SET_RATE_PARENT, 808 }, 809 }; 810 811 static struct clk_regmap axg_pcie_ref = { 812 .data = &(struct clk_regmap_mux_data){ 813 .offset = HHI_PCIE_PLL_CNTL6, 814 .mask = 0x1, 815 .shift = 1, 816 /* skip the parent 0, reserved for debug */ 817 .table = (u32[]){ 1 }, 818 }, 819 .hw.init = &(struct clk_init_data){ 820 .name = "pcie_ref", 821 .ops = &clk_regmap_mux_ops, 822 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 }, 826 }; 827 828 static struct clk_regmap axg_pcie_cml_en0 = { 829 .data = &(struct clk_regmap_gate_data){ 830 .offset = HHI_PCIE_PLL_CNTL6, 831 .bit_idx = 4, 832 }, 833 .hw.init = &(struct clk_init_data) { 834 .name = "pcie_cml_en0", 835 .ops = &clk_regmap_gate_ops, 836 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 837 .num_parents = 1, 838 .flags = CLK_SET_RATE_PARENT, 839 840 }, 841 }; 842 843 static struct clk_regmap axg_pcie_cml_en1 = { 844 .data = &(struct clk_regmap_gate_data){ 845 .offset = HHI_PCIE_PLL_CNTL6, 846 .bit_idx = 3, 847 }, 848 .hw.init = &(struct clk_init_data) { 849 .name = "pcie_cml_en1", 850 .ops = &clk_regmap_gate_ops, 851 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 852 .num_parents = 1, 853 .flags = CLK_SET_RATE_PARENT, 854 }, 855 }; 856 857 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 858 static const struct clk_parent_data clk81_parent_data[] = { 859 { .fw_name = "xtal", }, 860 { .hw = &axg_fclk_div7.hw }, 861 { .hw = &axg_mpll1.hw }, 862 { .hw = &axg_mpll2.hw }, 863 { .hw = &axg_fclk_div4.hw }, 864 { .hw = &axg_fclk_div3.hw }, 865 { .hw = &axg_fclk_div5.hw }, 866 }; 867 868 static struct clk_regmap axg_mpeg_clk_sel = { 869 .data = &(struct clk_regmap_mux_data){ 870 .offset = HHI_MPEG_CLK_CNTL, 871 .mask = 0x7, 872 .shift = 12, 873 .table = mux_table_clk81, 874 }, 875 .hw.init = &(struct clk_init_data){ 876 .name = "mpeg_clk_sel", 877 .ops = &clk_regmap_mux_ro_ops, 878 .parent_data = clk81_parent_data, 879 .num_parents = ARRAY_SIZE(clk81_parent_data), 880 }, 881 }; 882 883 static struct clk_regmap axg_mpeg_clk_div = { 884 .data = &(struct clk_regmap_div_data){ 885 .offset = HHI_MPEG_CLK_CNTL, 886 .shift = 0, 887 .width = 7, 888 }, 889 .hw.init = &(struct clk_init_data){ 890 .name = "mpeg_clk_div", 891 .ops = &clk_regmap_divider_ops, 892 .parent_hws = (const struct clk_hw *[]) { 893 &axg_mpeg_clk_sel.hw 894 }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT, 897 }, 898 }; 899 900 static struct clk_regmap axg_clk81 = { 901 .data = &(struct clk_regmap_gate_data){ 902 .offset = HHI_MPEG_CLK_CNTL, 903 .bit_idx = 7, 904 }, 905 .hw.init = &(struct clk_init_data){ 906 .name = "clk81", 907 .ops = &clk_regmap_gate_ops, 908 .parent_hws = (const struct clk_hw *[]) { 909 &axg_mpeg_clk_div.hw 910 }, 911 .num_parents = 1, 912 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 913 }, 914 }; 915 916 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = { 917 { .fw_name = "xtal", }, 918 { .hw = &axg_fclk_div2.hw }, 919 { .hw = &axg_fclk_div3.hw }, 920 { .hw = &axg_fclk_div5.hw }, 921 { .hw = &axg_fclk_div7.hw }, 922 /* 923 * Following these parent clocks, we should also have had mpll2, mpll3 924 * and gp0_pll but these clocks are too precious to be used here. All 925 * the necessary rates for MMC and NAND operation can be acheived using 926 * xtal or fclk_div clocks 927 */ 928 }; 929 930 /* SDcard clock */ 931 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 932 .data = &(struct clk_regmap_mux_data){ 933 .offset = HHI_SD_EMMC_CLK_CNTL, 934 .mask = 0x7, 935 .shift = 25, 936 }, 937 .hw.init = &(struct clk_init_data) { 938 .name = "sd_emmc_b_clk0_sel", 939 .ops = &clk_regmap_mux_ops, 940 .parent_data = axg_sd_emmc_clk0_parent_data, 941 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 942 .flags = CLK_SET_RATE_PARENT, 943 }, 944 }; 945 946 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 947 .data = &(struct clk_regmap_div_data){ 948 .offset = HHI_SD_EMMC_CLK_CNTL, 949 .shift = 16, 950 .width = 7, 951 .flags = CLK_DIVIDER_ROUND_CLOSEST, 952 }, 953 .hw.init = &(struct clk_init_data) { 954 .name = "sd_emmc_b_clk0_div", 955 .ops = &clk_regmap_divider_ops, 956 .parent_hws = (const struct clk_hw *[]) { 957 &axg_sd_emmc_b_clk0_sel.hw 958 }, 959 .num_parents = 1, 960 .flags = CLK_SET_RATE_PARENT, 961 }, 962 }; 963 964 static struct clk_regmap axg_sd_emmc_b_clk0 = { 965 .data = &(struct clk_regmap_gate_data){ 966 .offset = HHI_SD_EMMC_CLK_CNTL, 967 .bit_idx = 23, 968 }, 969 .hw.init = &(struct clk_init_data){ 970 .name = "sd_emmc_b_clk0", 971 .ops = &clk_regmap_gate_ops, 972 .parent_hws = (const struct clk_hw *[]) { 973 &axg_sd_emmc_b_clk0_div.hw 974 }, 975 .num_parents = 1, 976 .flags = CLK_SET_RATE_PARENT, 977 }, 978 }; 979 980 /* EMMC/NAND clock */ 981 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 982 .data = &(struct clk_regmap_mux_data){ 983 .offset = HHI_NAND_CLK_CNTL, 984 .mask = 0x7, 985 .shift = 9, 986 }, 987 .hw.init = &(struct clk_init_data) { 988 .name = "sd_emmc_c_clk0_sel", 989 .ops = &clk_regmap_mux_ops, 990 .parent_data = axg_sd_emmc_clk0_parent_data, 991 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 992 .flags = CLK_SET_RATE_PARENT, 993 }, 994 }; 995 996 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 997 .data = &(struct clk_regmap_div_data){ 998 .offset = HHI_NAND_CLK_CNTL, 999 .shift = 0, 1000 .width = 7, 1001 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1002 }, 1003 .hw.init = &(struct clk_init_data) { 1004 .name = "sd_emmc_c_clk0_div", 1005 .ops = &clk_regmap_divider_ops, 1006 .parent_hws = (const struct clk_hw *[]) { 1007 &axg_sd_emmc_c_clk0_sel.hw 1008 }, 1009 .num_parents = 1, 1010 .flags = CLK_SET_RATE_PARENT, 1011 }, 1012 }; 1013 1014 static struct clk_regmap axg_sd_emmc_c_clk0 = { 1015 .data = &(struct clk_regmap_gate_data){ 1016 .offset = HHI_NAND_CLK_CNTL, 1017 .bit_idx = 7, 1018 }, 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "sd_emmc_c_clk0", 1021 .ops = &clk_regmap_gate_ops, 1022 .parent_hws = (const struct clk_hw *[]) { 1023 &axg_sd_emmc_c_clk0_div.hw 1024 }, 1025 .num_parents = 1, 1026 .flags = CLK_SET_RATE_PARENT, 1027 }, 1028 }; 1029 1030 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1031 9, 10, 11, 13, 14, }; 1032 static const struct clk_parent_data gen_clk_parent_data[] = { 1033 { .fw_name = "xtal", }, 1034 { .hw = &axg_hifi_pll.hw }, 1035 { .hw = &axg_mpll0.hw }, 1036 { .hw = &axg_mpll1.hw }, 1037 { .hw = &axg_mpll2.hw }, 1038 { .hw = &axg_mpll3.hw }, 1039 { .hw = &axg_fclk_div4.hw }, 1040 { .hw = &axg_fclk_div3.hw }, 1041 { .hw = &axg_fclk_div5.hw }, 1042 { .hw = &axg_fclk_div7.hw }, 1043 { .hw = &axg_gp0_pll.hw }, 1044 }; 1045 1046 static struct clk_regmap axg_gen_clk_sel = { 1047 .data = &(struct clk_regmap_mux_data){ 1048 .offset = HHI_GEN_CLK_CNTL, 1049 .mask = 0xf, 1050 .shift = 12, 1051 .table = mux_table_gen_clk, 1052 }, 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "gen_clk_sel", 1055 .ops = &clk_regmap_mux_ops, 1056 /* 1057 * bits 15:12 selects from 14 possible parents: 1058 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1059 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1060 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1061 */ 1062 .parent_data = gen_clk_parent_data, 1063 .num_parents = ARRAY_SIZE(gen_clk_parent_data), 1064 }, 1065 }; 1066 1067 static struct clk_regmap axg_gen_clk_div = { 1068 .data = &(struct clk_regmap_div_data){ 1069 .offset = HHI_GEN_CLK_CNTL, 1070 .shift = 0, 1071 .width = 11, 1072 }, 1073 .hw.init = &(struct clk_init_data){ 1074 .name = "gen_clk_div", 1075 .ops = &clk_regmap_divider_ops, 1076 .parent_hws = (const struct clk_hw *[]) { 1077 &axg_gen_clk_sel.hw 1078 }, 1079 .num_parents = 1, 1080 .flags = CLK_SET_RATE_PARENT, 1081 }, 1082 }; 1083 1084 static struct clk_regmap axg_gen_clk = { 1085 .data = &(struct clk_regmap_gate_data){ 1086 .offset = HHI_GEN_CLK_CNTL, 1087 .bit_idx = 7, 1088 }, 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "gen_clk", 1091 .ops = &clk_regmap_gate_ops, 1092 .parent_hws = (const struct clk_hw *[]) { 1093 &axg_gen_clk_div.hw 1094 }, 1095 .num_parents = 1, 1096 .flags = CLK_SET_RATE_PARENT, 1097 }, 1098 }; 1099 1100 #define MESON_GATE(_name, _reg, _bit) \ 1101 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) 1102 1103 /* Everything Else (EE) domain gates */ 1104 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1105 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1106 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1107 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 1108 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 1109 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 1110 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 1111 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 1112 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 1113 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 1114 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 1115 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 1116 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 1117 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 1118 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 1119 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 1120 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 1121 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 1122 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 1123 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 1124 1125 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 1126 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 1127 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 1128 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 1129 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 1130 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 1131 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 1132 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 1133 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 1134 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 1135 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 1136 1137 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1138 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1139 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1140 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 1141 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 1142 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1143 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1144 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1145 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29); 1146 1147 /* Always On (AO) domain gates */ 1148 1149 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 1150 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 1151 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 1152 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 1153 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 1154 1155 /* Array of all clocks provided by this provider */ 1156 1157 static struct clk_hw_onecell_data axg_hw_onecell_data = { 1158 .hws = { 1159 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1160 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1161 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1162 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1163 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1164 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1165 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1166 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1167 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1168 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1169 [CLKID_CLK81] = &axg_clk81.hw, 1170 [CLKID_MPLL0] = &axg_mpll0.hw, 1171 [CLKID_MPLL1] = &axg_mpll1.hw, 1172 [CLKID_MPLL2] = &axg_mpll2.hw, 1173 [CLKID_MPLL3] = &axg_mpll3.hw, 1174 [CLKID_DDR] = &axg_ddr.hw, 1175 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1176 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1177 [CLKID_ISA] = &axg_isa.hw, 1178 [CLKID_PL301] = &axg_pl301.hw, 1179 [CLKID_PERIPHS] = &axg_periphs.hw, 1180 [CLKID_SPICC0] = &axg_spicc_0.hw, 1181 [CLKID_I2C] = &axg_i2c.hw, 1182 [CLKID_RNG0] = &axg_rng0.hw, 1183 [CLKID_UART0] = &axg_uart0.hw, 1184 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1185 [CLKID_SPICC1] = &axg_spicc_1.hw, 1186 [CLKID_PCIE_A] = &axg_pcie_a.hw, 1187 [CLKID_PCIE_B] = &axg_pcie_b.hw, 1188 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1189 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1190 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1191 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1192 [CLKID_DMA] = &axg_dma.hw, 1193 [CLKID_SPI] = &axg_spi.hw, 1194 [CLKID_AUDIO] = &axg_audio.hw, 1195 [CLKID_ETH] = &axg_eth_core.hw, 1196 [CLKID_UART1] = &axg_uart1.hw, 1197 [CLKID_G2D] = &axg_g2d.hw, 1198 [CLKID_USB0] = &axg_usb0.hw, 1199 [CLKID_USB1] = &axg_usb1.hw, 1200 [CLKID_RESET] = &axg_reset.hw, 1201 [CLKID_USB] = &axg_usb_general.hw, 1202 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1203 [CLKID_EFUSE] = &axg_efuse.hw, 1204 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1205 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1206 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1207 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1208 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1209 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1210 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1211 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1212 [CLKID_GIC] = &axg_gic.hw, 1213 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1214 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1215 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1216 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1217 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1218 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1219 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1220 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1221 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1222 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1223 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1224 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1225 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1226 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1227 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1228 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1229 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1230 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1231 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1232 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1233 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1234 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1235 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1236 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1237 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1238 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1239 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1240 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw, 1241 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1242 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1243 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1244 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1245 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1246 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1247 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1248 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1249 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1250 [NR_CLKS] = NULL, 1251 }, 1252 .num = NR_CLKS, 1253 }; 1254 1255 /* Convenience table to populate regmap in .probe */ 1256 static struct clk_regmap *const axg_clk_regmaps[] = { 1257 &axg_clk81, 1258 &axg_ddr, 1259 &axg_audio_locker, 1260 &axg_mipi_dsi_host, 1261 &axg_isa, 1262 &axg_pl301, 1263 &axg_periphs, 1264 &axg_spicc_0, 1265 &axg_i2c, 1266 &axg_rng0, 1267 &axg_uart0, 1268 &axg_mipi_dsi_phy, 1269 &axg_spicc_1, 1270 &axg_pcie_a, 1271 &axg_pcie_b, 1272 &axg_hiu_reg, 1273 &axg_assist_misc, 1274 &axg_emmc_b, 1275 &axg_emmc_c, 1276 &axg_dma, 1277 &axg_spi, 1278 &axg_audio, 1279 &axg_eth_core, 1280 &axg_uart1, 1281 &axg_g2d, 1282 &axg_usb0, 1283 &axg_usb1, 1284 &axg_reset, 1285 &axg_usb_general, 1286 &axg_ahb_arb0, 1287 &axg_efuse, 1288 &axg_boot_rom, 1289 &axg_ahb_data_bus, 1290 &axg_ahb_ctrl_bus, 1291 &axg_usb1_to_ddr, 1292 &axg_usb0_to_ddr, 1293 &axg_mmc_pclk, 1294 &axg_vpu_intr, 1295 &axg_sec_ahb_ahb3_bridge, 1296 &axg_gic, 1297 &axg_ao_media_cpu, 1298 &axg_ao_ahb_sram, 1299 &axg_ao_ahb_bus, 1300 &axg_ao_iface, 1301 &axg_ao_i2c, 1302 &axg_sd_emmc_b_clk0, 1303 &axg_sd_emmc_c_clk0, 1304 &axg_mpeg_clk_div, 1305 &axg_sd_emmc_b_clk0_div, 1306 &axg_sd_emmc_c_clk0_div, 1307 &axg_mpeg_clk_sel, 1308 &axg_sd_emmc_b_clk0_sel, 1309 &axg_sd_emmc_c_clk0_sel, 1310 &axg_mpll0, 1311 &axg_mpll1, 1312 &axg_mpll2, 1313 &axg_mpll3, 1314 &axg_mpll0_div, 1315 &axg_mpll1_div, 1316 &axg_mpll2_div, 1317 &axg_mpll3_div, 1318 &axg_fixed_pll, 1319 &axg_sys_pll, 1320 &axg_gp0_pll, 1321 &axg_hifi_pll, 1322 &axg_mpll_prediv, 1323 &axg_fclk_div2, 1324 &axg_fclk_div3, 1325 &axg_fclk_div4, 1326 &axg_fclk_div5, 1327 &axg_fclk_div7, 1328 &axg_pcie_pll_dco, 1329 &axg_pcie_pll_od, 1330 &axg_pcie_pll, 1331 &axg_pcie_mux, 1332 &axg_pcie_ref, 1333 &axg_pcie_cml_en0, 1334 &axg_pcie_cml_en1, 1335 &axg_mipi_enable, 1336 &axg_gen_clk_sel, 1337 &axg_gen_clk_div, 1338 &axg_gen_clk, 1339 &axg_fixed_pll_dco, 1340 &axg_sys_pll_dco, 1341 &axg_gp0_pll_dco, 1342 &axg_hifi_pll_dco, 1343 &axg_pcie_pll_dco, 1344 &axg_pcie_pll_od, 1345 }; 1346 1347 static const struct meson_eeclkc_data axg_clkc_data = { 1348 .regmap_clks = axg_clk_regmaps, 1349 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 1350 .hw_onecell_data = &axg_hw_onecell_data, 1351 }; 1352 1353 1354 static const struct of_device_id clkc_match_table[] = { 1355 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 1356 {} 1357 }; 1358 MODULE_DEVICE_TABLE(of, clkc_match_table); 1359 1360 static struct platform_driver axg_driver = { 1361 .probe = meson_eeclkc_probe, 1362 .driver = { 1363 .name = "axg-clkc", 1364 .of_match_table = clkc_match_table, 1365 }, 1366 }; 1367 1368 module_platform_driver(axg_driver); 1369 MODULE_LICENSE("GPL v2"); 1370