1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __AXG_AUDIO_CLKC_H 8*4882a593Smuzhiyun #define __AXG_AUDIO_CLKC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Audio Clock register offsets 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Register offsets from the datasheet must be multiplied by 4 before 14*4882a593Smuzhiyun * to get the right offset 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define AUDIO_CLK_GATE_EN 0x000 17*4882a593Smuzhiyun #define AUDIO_MCLK_A_CTRL 0x004 18*4882a593Smuzhiyun #define AUDIO_MCLK_B_CTRL 0x008 19*4882a593Smuzhiyun #define AUDIO_MCLK_C_CTRL 0x00C 20*4882a593Smuzhiyun #define AUDIO_MCLK_D_CTRL 0x010 21*4882a593Smuzhiyun #define AUDIO_MCLK_E_CTRL 0x014 22*4882a593Smuzhiyun #define AUDIO_MCLK_F_CTRL 0x018 23*4882a593Smuzhiyun #define AUDIO_MST_PAD_CTRL0 0x01c 24*4882a593Smuzhiyun #define AUDIO_MST_PAD_CTRL1 0x020 25*4882a593Smuzhiyun #define AUDIO_SW_RESET 0x024 26*4882a593Smuzhiyun #define AUDIO_MST_A_SCLK_CTRL0 0x040 27*4882a593Smuzhiyun #define AUDIO_MST_A_SCLK_CTRL1 0x044 28*4882a593Smuzhiyun #define AUDIO_MST_B_SCLK_CTRL0 0x048 29*4882a593Smuzhiyun #define AUDIO_MST_B_SCLK_CTRL1 0x04C 30*4882a593Smuzhiyun #define AUDIO_MST_C_SCLK_CTRL0 0x050 31*4882a593Smuzhiyun #define AUDIO_MST_C_SCLK_CTRL1 0x054 32*4882a593Smuzhiyun #define AUDIO_MST_D_SCLK_CTRL0 0x058 33*4882a593Smuzhiyun #define AUDIO_MST_D_SCLK_CTRL1 0x05C 34*4882a593Smuzhiyun #define AUDIO_MST_E_SCLK_CTRL0 0x060 35*4882a593Smuzhiyun #define AUDIO_MST_E_SCLK_CTRL1 0x064 36*4882a593Smuzhiyun #define AUDIO_MST_F_SCLK_CTRL0 0x068 37*4882a593Smuzhiyun #define AUDIO_MST_F_SCLK_CTRL1 0x06C 38*4882a593Smuzhiyun #define AUDIO_CLK_TDMIN_A_CTRL 0x080 39*4882a593Smuzhiyun #define AUDIO_CLK_TDMIN_B_CTRL 0x084 40*4882a593Smuzhiyun #define AUDIO_CLK_TDMIN_C_CTRL 0x088 41*4882a593Smuzhiyun #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 42*4882a593Smuzhiyun #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 43*4882a593Smuzhiyun #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 44*4882a593Smuzhiyun #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 45*4882a593Smuzhiyun #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 46*4882a593Smuzhiyun #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 47*4882a593Smuzhiyun #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 48*4882a593Smuzhiyun #define AUDIO_CLK_LOCKER_CTRL 0x0A8 49*4882a593Smuzhiyun #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 50*4882a593Smuzhiyun #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 51*4882a593Smuzhiyun #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* SM1 introduce new register and some shifts :( */ 54*4882a593Smuzhiyun #define AUDIO_CLK_GATE_EN1 0x004 55*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_A_CTRL 0x008 56*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_C_CTRL 0x010 58*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_D_CTRL 0x014 59*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_E_CTRL 0x018 60*4882a593Smuzhiyun #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61*4882a593Smuzhiyun #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62*4882a593Smuzhiyun #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63*4882a593Smuzhiyun #define AUDIO_SM1_SW_RESET0 0x028 64*4882a593Smuzhiyun #define AUDIO_SM1_SW_RESET1 0x02C 65*4882a593Smuzhiyun #define AUDIO_CLK81_CTRL 0x030 66*4882a593Smuzhiyun #define AUDIO_CLK81_EN 0x034 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * CLKID index values 69*4882a593Smuzhiyun * These indices are entirely contrived and do not map onto the hardware. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define AUD_CLKID_MST_A_MCLK_SEL 59 73*4882a593Smuzhiyun #define AUD_CLKID_MST_B_MCLK_SEL 60 74*4882a593Smuzhiyun #define AUD_CLKID_MST_C_MCLK_SEL 61 75*4882a593Smuzhiyun #define AUD_CLKID_MST_D_MCLK_SEL 62 76*4882a593Smuzhiyun #define AUD_CLKID_MST_E_MCLK_SEL 63 77*4882a593Smuzhiyun #define AUD_CLKID_MST_F_MCLK_SEL 64 78*4882a593Smuzhiyun #define AUD_CLKID_MST_A_MCLK_DIV 65 79*4882a593Smuzhiyun #define AUD_CLKID_MST_B_MCLK_DIV 66 80*4882a593Smuzhiyun #define AUD_CLKID_MST_C_MCLK_DIV 67 81*4882a593Smuzhiyun #define AUD_CLKID_MST_D_MCLK_DIV 68 82*4882a593Smuzhiyun #define AUD_CLKID_MST_E_MCLK_DIV 69 83*4882a593Smuzhiyun #define AUD_CLKID_MST_F_MCLK_DIV 70 84*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_CLK_SEL 71 85*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_CLK_DIV 72 86*4882a593Smuzhiyun #define AUD_CLKID_SPDIFIN_CLK_SEL 73 87*4882a593Smuzhiyun #define AUD_CLKID_SPDIFIN_CLK_DIV 74 88*4882a593Smuzhiyun #define AUD_CLKID_PDM_DCLK_SEL 75 89*4882a593Smuzhiyun #define AUD_CLKID_PDM_DCLK_DIV 76 90*4882a593Smuzhiyun #define AUD_CLKID_PDM_SYSCLK_SEL 77 91*4882a593Smuzhiyun #define AUD_CLKID_PDM_SYSCLK_DIV 78 92*4882a593Smuzhiyun #define AUD_CLKID_MST_A_SCLK_PRE_EN 92 93*4882a593Smuzhiyun #define AUD_CLKID_MST_B_SCLK_PRE_EN 93 94*4882a593Smuzhiyun #define AUD_CLKID_MST_C_SCLK_PRE_EN 94 95*4882a593Smuzhiyun #define AUD_CLKID_MST_D_SCLK_PRE_EN 95 96*4882a593Smuzhiyun #define AUD_CLKID_MST_E_SCLK_PRE_EN 96 97*4882a593Smuzhiyun #define AUD_CLKID_MST_F_SCLK_PRE_EN 97 98*4882a593Smuzhiyun #define AUD_CLKID_MST_A_SCLK_DIV 98 99*4882a593Smuzhiyun #define AUD_CLKID_MST_B_SCLK_DIV 99 100*4882a593Smuzhiyun #define AUD_CLKID_MST_C_SCLK_DIV 100 101*4882a593Smuzhiyun #define AUD_CLKID_MST_D_SCLK_DIV 101 102*4882a593Smuzhiyun #define AUD_CLKID_MST_E_SCLK_DIV 102 103*4882a593Smuzhiyun #define AUD_CLKID_MST_F_SCLK_DIV 103 104*4882a593Smuzhiyun #define AUD_CLKID_MST_A_SCLK_POST_EN 104 105*4882a593Smuzhiyun #define AUD_CLKID_MST_B_SCLK_POST_EN 105 106*4882a593Smuzhiyun #define AUD_CLKID_MST_C_SCLK_POST_EN 106 107*4882a593Smuzhiyun #define AUD_CLKID_MST_D_SCLK_POST_EN 107 108*4882a593Smuzhiyun #define AUD_CLKID_MST_E_SCLK_POST_EN 108 109*4882a593Smuzhiyun #define AUD_CLKID_MST_F_SCLK_POST_EN 109 110*4882a593Smuzhiyun #define AUD_CLKID_MST_A_LRCLK_DIV 110 111*4882a593Smuzhiyun #define AUD_CLKID_MST_B_LRCLK_DIV 111 112*4882a593Smuzhiyun #define AUD_CLKID_MST_C_LRCLK_DIV 112 113*4882a593Smuzhiyun #define AUD_CLKID_MST_D_LRCLK_DIV 113 114*4882a593Smuzhiyun #define AUD_CLKID_MST_E_LRCLK_DIV 114 115*4882a593Smuzhiyun #define AUD_CLKID_MST_F_LRCLK_DIV 115 116*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 117*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 118*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 119*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 120*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 121*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 122*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 123*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 124*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 125*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 126*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 127*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 128*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 129*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 130*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 131*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 132*4882a593Smuzhiyun #define AUD_CLKID_CLK81_EN 173 133*4882a593Smuzhiyun #define AUD_CLKID_SYSCLK_A_DIV 174 134*4882a593Smuzhiyun #define AUD_CLKID_SYSCLK_B_DIV 175 135*4882a593Smuzhiyun #define AUD_CLKID_SYSCLK_A_EN 176 136*4882a593Smuzhiyun #define AUD_CLKID_SYSCLK_B_EN 177 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* include the CLKIDs which are part of the DT bindings */ 139*4882a593Smuzhiyun #include <dt-bindings/clock/axg-audio-clkc.h> 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define NR_CLKS 178 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /*__AXG_AUDIO_CLKC_H */ 144