1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Owen Chen <owen.chen@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DRV_CLK_MTK_MUX_H 8*4882a593Smuzhiyun #define __DRV_CLK_MTK_MUX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/clk-provider.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct mtk_clk_mux { 13*4882a593Smuzhiyun struct clk_hw hw; 14*4882a593Smuzhiyun struct regmap *regmap; 15*4882a593Smuzhiyun const struct mtk_mux *data; 16*4882a593Smuzhiyun spinlock_t *lock; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct mtk_mux { 20*4882a593Smuzhiyun int id; 21*4882a593Smuzhiyun const char *name; 22*4882a593Smuzhiyun const char * const *parent_names; 23*4882a593Smuzhiyun unsigned int flags; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun u32 mux_ofs; 26*4882a593Smuzhiyun u32 set_ofs; 27*4882a593Smuzhiyun u32 clr_ofs; 28*4882a593Smuzhiyun u32 upd_ofs; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun u8 mux_shift; 31*4882a593Smuzhiyun u8 mux_width; 32*4882a593Smuzhiyun u8 gate_shift; 33*4882a593Smuzhiyun s8 upd_shift; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun const struct clk_ops *ops; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun signed char num_parents; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun extern const struct clk_ops mtk_mux_ops; 41*4882a593Smuzhiyun extern const struct clk_ops mtk_mux_clr_set_upd_ops; 42*4882a593Smuzhiyun extern const struct clk_ops mtk_mux_gate_ops; 43*4882a593Smuzhiyun extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ 46*4882a593Smuzhiyun _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ 47*4882a593Smuzhiyun _gate, _upd_ofs, _upd, _flags, _ops) { \ 48*4882a593Smuzhiyun .id = _id, \ 49*4882a593Smuzhiyun .name = _name, \ 50*4882a593Smuzhiyun .mux_ofs = _mux_ofs, \ 51*4882a593Smuzhiyun .set_ofs = _mux_set_ofs, \ 52*4882a593Smuzhiyun .clr_ofs = _mux_clr_ofs, \ 53*4882a593Smuzhiyun .upd_ofs = _upd_ofs, \ 54*4882a593Smuzhiyun .mux_shift = _shift, \ 55*4882a593Smuzhiyun .mux_width = _width, \ 56*4882a593Smuzhiyun .gate_shift = _gate, \ 57*4882a593Smuzhiyun .upd_shift = _upd, \ 58*4882a593Smuzhiyun .parent_names = _parents, \ 59*4882a593Smuzhiyun .num_parents = ARRAY_SIZE(_parents), \ 60*4882a593Smuzhiyun .flags = _flags, \ 61*4882a593Smuzhiyun .ops = &_ops, \ 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ 65*4882a593Smuzhiyun _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ 66*4882a593Smuzhiyun _gate, _upd_ofs, _upd, _flags) \ 67*4882a593Smuzhiyun GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ 68*4882a593Smuzhiyun _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ 69*4882a593Smuzhiyun _gate, _upd_ofs, _upd, _flags, \ 70*4882a593Smuzhiyun mtk_mux_gate_clr_set_upd_ops) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ 73*4882a593Smuzhiyun _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ 74*4882a593Smuzhiyun _gate, _upd_ofs, _upd) \ 75*4882a593Smuzhiyun MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ 76*4882a593Smuzhiyun _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ 77*4882a593Smuzhiyun _width, _gate, _upd_ofs, _upd, \ 78*4882a593Smuzhiyun CLK_SET_RATE_PARENT) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, 81*4882a593Smuzhiyun struct regmap *regmap, 82*4882a593Smuzhiyun spinlock_t *lock); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int mtk_clk_register_muxes(const struct mtk_mux *muxes, 85*4882a593Smuzhiyun int num, struct device_node *node, 86*4882a593Smuzhiyun spinlock_t *lock, 87*4882a593Smuzhiyun struct clk_onecell_data *clk_data); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* __DRV_CLK_MTK_MUX_H */ 90