1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc.
4*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/of.h>
8*4882a593Smuzhiyun #include <linux/of_address.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/clkdev.h>
14*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
15*4882a593Smuzhiyun #include <linux/device.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "clk-mtk.h"
18*4882a593Smuzhiyun #include "clk-gate.h"
19*4882a593Smuzhiyun
mtk_alloc_clk_data(unsigned int clk_num)20*4882a593Smuzhiyun struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun int i;
23*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
26*4882a593Smuzhiyun if (!clk_data)
27*4882a593Smuzhiyun return NULL;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
30*4882a593Smuzhiyun if (!clk_data->clks)
31*4882a593Smuzhiyun goto err_out;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun clk_data->clk_num = clk_num;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun for (i = 0; i < clk_num; i++)
36*4882a593Smuzhiyun clk_data->clks[i] = ERR_PTR(-ENOENT);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return clk_data;
39*4882a593Smuzhiyun err_out:
40*4882a593Smuzhiyun kfree(clk_data);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return NULL;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
mtk_clk_register_fixed_clks(const struct mtk_fixed_clk * clks,int num,struct clk_onecell_data * clk_data)45*4882a593Smuzhiyun void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
46*4882a593Smuzhiyun int num, struct clk_onecell_data *clk_data)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun int i;
49*4882a593Smuzhiyun struct clk *clk;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun for (i = 0; i < num; i++) {
52*4882a593Smuzhiyun const struct mtk_fixed_clk *rc = &clks[i];
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id]))
55*4882a593Smuzhiyun continue;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0,
58*4882a593Smuzhiyun rc->rate);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (IS_ERR(clk)) {
61*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
62*4882a593Smuzhiyun rc->name, PTR_ERR(clk));
63*4882a593Smuzhiyun continue;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (clk_data)
67*4882a593Smuzhiyun clk_data->clks[rc->id] = clk;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
mtk_clk_register_factors(const struct mtk_fixed_factor * clks,int num,struct clk_onecell_data * clk_data)71*4882a593Smuzhiyun void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
72*4882a593Smuzhiyun int num, struct clk_onecell_data *clk_data)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun int i;
75*4882a593Smuzhiyun struct clk *clk;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun for (i = 0; i < num; i++) {
78*4882a593Smuzhiyun const struct mtk_fixed_factor *ff = &clks[i];
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id]))
81*4882a593Smuzhiyun continue;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
84*4882a593Smuzhiyun CLK_SET_RATE_PARENT, ff->mult, ff->div);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (IS_ERR(clk)) {
87*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
88*4882a593Smuzhiyun ff->name, PTR_ERR(clk));
89*4882a593Smuzhiyun continue;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (clk_data)
93*4882a593Smuzhiyun clk_data->clks[ff->id] = clk;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
mtk_clk_register_gates_with_dev(struct device_node * node,const struct mtk_gate * clks,int num,struct clk_onecell_data * clk_data,struct device * dev)97*4882a593Smuzhiyun int mtk_clk_register_gates_with_dev(struct device_node *node,
98*4882a593Smuzhiyun const struct mtk_gate *clks,
99*4882a593Smuzhiyun int num, struct clk_onecell_data *clk_data,
100*4882a593Smuzhiyun struct device *dev)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun int i;
103*4882a593Smuzhiyun struct clk *clk;
104*4882a593Smuzhiyun struct regmap *regmap;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (!clk_data)
107*4882a593Smuzhiyun return -ENOMEM;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun regmap = syscon_node_to_regmap(node);
110*4882a593Smuzhiyun if (IS_ERR(regmap)) {
111*4882a593Smuzhiyun pr_err("Cannot find regmap for %pOF: %ld\n", node,
112*4882a593Smuzhiyun PTR_ERR(regmap));
113*4882a593Smuzhiyun return PTR_ERR(regmap);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun for (i = 0; i < num; i++) {
117*4882a593Smuzhiyun const struct mtk_gate *gate = &clks[i];
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
120*4882a593Smuzhiyun continue;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun clk = mtk_clk_register_gate(gate->name, gate->parent_name,
123*4882a593Smuzhiyun regmap,
124*4882a593Smuzhiyun gate->regs->set_ofs,
125*4882a593Smuzhiyun gate->regs->clr_ofs,
126*4882a593Smuzhiyun gate->regs->sta_ofs,
127*4882a593Smuzhiyun gate->shift, gate->ops, gate->flags, dev);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (IS_ERR(clk)) {
130*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
131*4882a593Smuzhiyun gate->name, PTR_ERR(clk));
132*4882a593Smuzhiyun continue;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun clk_data->clks[gate->id] = clk;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
mtk_clk_register_gates(struct device_node * node,const struct mtk_gate * clks,int num,struct clk_onecell_data * clk_data)141*4882a593Smuzhiyun int mtk_clk_register_gates(struct device_node *node,
142*4882a593Smuzhiyun const struct mtk_gate *clks,
143*4882a593Smuzhiyun int num, struct clk_onecell_data *clk_data)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return mtk_clk_register_gates_with_dev(node,
146*4882a593Smuzhiyun clks, num, clk_data, NULL);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
mtk_clk_register_composite(const struct mtk_composite * mc,void __iomem * base,spinlock_t * lock)149*4882a593Smuzhiyun struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
150*4882a593Smuzhiyun void __iomem *base, spinlock_t *lock)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct clk *clk;
153*4882a593Smuzhiyun struct clk_mux *mux = NULL;
154*4882a593Smuzhiyun struct clk_gate *gate = NULL;
155*4882a593Smuzhiyun struct clk_divider *div = NULL;
156*4882a593Smuzhiyun struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
157*4882a593Smuzhiyun const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
158*4882a593Smuzhiyun const char * const *parent_names;
159*4882a593Smuzhiyun const char *parent;
160*4882a593Smuzhiyun int num_parents;
161*4882a593Smuzhiyun int ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (mc->mux_shift >= 0) {
164*4882a593Smuzhiyun mux = kzalloc(sizeof(*mux), GFP_KERNEL);
165*4882a593Smuzhiyun if (!mux)
166*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun mux->reg = base + mc->mux_reg;
169*4882a593Smuzhiyun mux->mask = BIT(mc->mux_width) - 1;
170*4882a593Smuzhiyun mux->shift = mc->mux_shift;
171*4882a593Smuzhiyun mux->lock = lock;
172*4882a593Smuzhiyun mux->flags = mc->mux_flags;
173*4882a593Smuzhiyun mux_hw = &mux->hw;
174*4882a593Smuzhiyun mux_ops = &clk_mux_ops;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun parent_names = mc->parent_names;
177*4882a593Smuzhiyun num_parents = mc->num_parents;
178*4882a593Smuzhiyun } else {
179*4882a593Smuzhiyun parent = mc->parent;
180*4882a593Smuzhiyun parent_names = &parent;
181*4882a593Smuzhiyun num_parents = 1;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (mc->gate_shift >= 0) {
185*4882a593Smuzhiyun gate = kzalloc(sizeof(*gate), GFP_KERNEL);
186*4882a593Smuzhiyun if (!gate) {
187*4882a593Smuzhiyun ret = -ENOMEM;
188*4882a593Smuzhiyun goto err_out;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun gate->reg = base + mc->gate_reg;
192*4882a593Smuzhiyun gate->bit_idx = mc->gate_shift;
193*4882a593Smuzhiyun gate->flags = CLK_GATE_SET_TO_DISABLE;
194*4882a593Smuzhiyun gate->lock = lock;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun gate_hw = &gate->hw;
197*4882a593Smuzhiyun gate_ops = &clk_gate_ops;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (mc->divider_shift >= 0) {
201*4882a593Smuzhiyun div = kzalloc(sizeof(*div), GFP_KERNEL);
202*4882a593Smuzhiyun if (!div) {
203*4882a593Smuzhiyun ret = -ENOMEM;
204*4882a593Smuzhiyun goto err_out;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun div->reg = base + mc->divider_reg;
208*4882a593Smuzhiyun div->shift = mc->divider_shift;
209*4882a593Smuzhiyun div->width = mc->divider_width;
210*4882a593Smuzhiyun div->lock = lock;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun div_hw = &div->hw;
213*4882a593Smuzhiyun div_ops = &clk_divider_ops;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
217*4882a593Smuzhiyun mux_hw, mux_ops,
218*4882a593Smuzhiyun div_hw, div_ops,
219*4882a593Smuzhiyun gate_hw, gate_ops,
220*4882a593Smuzhiyun mc->flags);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (IS_ERR(clk)) {
223*4882a593Smuzhiyun ret = PTR_ERR(clk);
224*4882a593Smuzhiyun goto err_out;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun return clk;
228*4882a593Smuzhiyun err_out:
229*4882a593Smuzhiyun kfree(div);
230*4882a593Smuzhiyun kfree(gate);
231*4882a593Smuzhiyun kfree(mux);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return ERR_PTR(ret);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
mtk_clk_register_composites(const struct mtk_composite * mcs,int num,void __iomem * base,spinlock_t * lock,struct clk_onecell_data * clk_data)236*4882a593Smuzhiyun void mtk_clk_register_composites(const struct mtk_composite *mcs,
237*4882a593Smuzhiyun int num, void __iomem *base, spinlock_t *lock,
238*4882a593Smuzhiyun struct clk_onecell_data *clk_data)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct clk *clk;
241*4882a593Smuzhiyun int i;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun for (i = 0; i < num; i++) {
244*4882a593Smuzhiyun const struct mtk_composite *mc = &mcs[i];
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id]))
247*4882a593Smuzhiyun continue;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun clk = mtk_clk_register_composite(mc, base, lock);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (IS_ERR(clk)) {
252*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
253*4882a593Smuzhiyun mc->name, PTR_ERR(clk));
254*4882a593Smuzhiyun continue;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (clk_data)
258*4882a593Smuzhiyun clk_data->clks[mc->id] = clk;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
mtk_clk_register_dividers(const struct mtk_clk_divider * mcds,int num,void __iomem * base,spinlock_t * lock,struct clk_onecell_data * clk_data)262*4882a593Smuzhiyun void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
263*4882a593Smuzhiyun int num, void __iomem *base, spinlock_t *lock,
264*4882a593Smuzhiyun struct clk_onecell_data *clk_data)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun struct clk *clk;
267*4882a593Smuzhiyun int i;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun for (i = 0; i < num; i++) {
270*4882a593Smuzhiyun const struct mtk_clk_divider *mcd = &mcds[i];
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
273*4882a593Smuzhiyun continue;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
276*4882a593Smuzhiyun mcd->flags, base + mcd->div_reg, mcd->div_shift,
277*4882a593Smuzhiyun mcd->div_width, mcd->clk_divider_flags, lock);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (IS_ERR(clk)) {
280*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
281*4882a593Smuzhiyun mcd->name, PTR_ERR(clk));
282*4882a593Smuzhiyun continue;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (clk_data)
286*4882a593Smuzhiyun clk_data->clks[mcd->id] = clk;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun }
289