1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc.
4*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com>
5*4882a593Smuzhiyun * Fabien Parent <fparent@baylibre.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_address.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "clk-mtk.h"
15*4882a593Smuzhiyun #include "clk-gate.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <dt-bindings/clock/mt8516-clk.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const struct mtk_gate_regs aud_cg_regs = {
20*4882a593Smuzhiyun .set_ofs = 0x0,
21*4882a593Smuzhiyun .clr_ofs = 0x0,
22*4882a593Smuzhiyun .sta_ofs = 0x0,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define GATE_AUD(_id, _name, _parent, _shift) { \
26*4882a593Smuzhiyun .id = _id, \
27*4882a593Smuzhiyun .name = _name, \
28*4882a593Smuzhiyun .parent_name = _parent, \
29*4882a593Smuzhiyun .regs = &aud_cg_regs, \
30*4882a593Smuzhiyun .shift = _shift, \
31*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_no_setclr, \
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct mtk_gate aud_clks[] __initconst = {
35*4882a593Smuzhiyun GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
36*4882a593Smuzhiyun GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
37*4882a593Smuzhiyun GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
38*4882a593Smuzhiyun GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
39*4882a593Smuzhiyun GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
40*4882a593Smuzhiyun GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
41*4882a593Smuzhiyun GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
42*4882a593Smuzhiyun GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
43*4882a593Smuzhiyun GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
44*4882a593Smuzhiyun GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
45*4882a593Smuzhiyun GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
46*4882a593Smuzhiyun GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
47*4882a593Smuzhiyun GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
mtk_audsys_init(struct device_node * node)50*4882a593Smuzhiyun static void __init mtk_audsys_init(struct device_node *node)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
53*4882a593Smuzhiyun int r;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
60*4882a593Smuzhiyun if (r)
61*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
62*4882a593Smuzhiyun __func__, r);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
66