1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2020 MediaTek Inc.
4*4882a593Smuzhiyun * Copyright (c) 2020 BayLibre, SAS
5*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com>
6*4882a593Smuzhiyun * Fabien Parent <fparent@baylibre.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "clk-mtk.h"
16*4882a593Smuzhiyun #include "clk-gate.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <dt-bindings/clock/mt8167-clk.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static const struct mtk_gate_regs vdec0_cg_regs = {
21*4882a593Smuzhiyun .set_ofs = 0x0,
22*4882a593Smuzhiyun .clr_ofs = 0x4,
23*4882a593Smuzhiyun .sta_ofs = 0x0,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const struct mtk_gate_regs vdec1_cg_regs = {
27*4882a593Smuzhiyun .set_ofs = 0x8,
28*4882a593Smuzhiyun .clr_ofs = 0xc,
29*4882a593Smuzhiyun .sta_ofs = 0x8,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define GATE_VDEC0_I(_id, _name, _parent, _shift) { \
33*4882a593Smuzhiyun .id = _id, \
34*4882a593Smuzhiyun .name = _name, \
35*4882a593Smuzhiyun .parent_name = _parent, \
36*4882a593Smuzhiyun .regs = &vdec0_cg_regs, \
37*4882a593Smuzhiyun .shift = _shift, \
38*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr_inv, \
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define GATE_VDEC1_I(_id, _name, _parent, _shift) { \
42*4882a593Smuzhiyun .id = _id, \
43*4882a593Smuzhiyun .name = _name, \
44*4882a593Smuzhiyun .parent_name = _parent, \
45*4882a593Smuzhiyun .regs = &vdec1_cg_regs, \
46*4882a593Smuzhiyun .shift = _shift, \
47*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr_inv, \
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct mtk_gate vdec_clks[] __initconst = {
51*4882a593Smuzhiyun /* VDEC0 */
52*4882a593Smuzhiyun GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
53*4882a593Smuzhiyun /* VDEC1 */
54*4882a593Smuzhiyun GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
mtk_vdecsys_init(struct device_node * node)57*4882a593Smuzhiyun static void __init mtk_vdecsys_init(struct device_node *node)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
60*4882a593Smuzhiyun int r;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (r)
69*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
70*4882a593Smuzhiyun __func__, r);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init);
74