xref: /OK3568_Linux_fs/kernel/drivers/clk/mediatek/clk-mt8167-mm.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2020 MediaTek Inc.
4*4882a593Smuzhiyun  * Copyright (c) 2020 BayLibre, SAS
5*4882a593Smuzhiyun  * Author: James Liao <jamesjj.liao@mediatek.com>
6*4882a593Smuzhiyun  *         Fabien Parent <fparent@baylibre.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include "clk-mtk.h"
16*4882a593Smuzhiyun #include "clk-gate.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <dt-bindings/clock/mt8167-clk.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static const struct mtk_gate_regs mm0_cg_regs = {
21*4882a593Smuzhiyun 	.set_ofs = 0x104,
22*4882a593Smuzhiyun 	.clr_ofs = 0x108,
23*4882a593Smuzhiyun 	.sta_ofs = 0x100,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static const struct mtk_gate_regs mm1_cg_regs = {
27*4882a593Smuzhiyun 	.set_ofs = 0x114,
28*4882a593Smuzhiyun 	.clr_ofs = 0x118,
29*4882a593Smuzhiyun 	.sta_ofs = 0x110,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define GATE_MM0(_id, _name, _parent, _shift) {		\
33*4882a593Smuzhiyun 		.id = _id,				\
34*4882a593Smuzhiyun 		.name = _name,				\
35*4882a593Smuzhiyun 		.parent_name = _parent,			\
36*4882a593Smuzhiyun 		.regs = &mm0_cg_regs,			\
37*4882a593Smuzhiyun 		.shift = _shift,			\
38*4882a593Smuzhiyun 		.ops = &mtk_clk_gate_ops_setclr,	\
39*4882a593Smuzhiyun 	}
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define GATE_MM1(_id, _name, _parent, _shift) {		\
42*4882a593Smuzhiyun 		.id = _id,				\
43*4882a593Smuzhiyun 		.name = _name,				\
44*4882a593Smuzhiyun 		.parent_name = _parent,			\
45*4882a593Smuzhiyun 		.regs = &mm1_cg_regs,			\
46*4882a593Smuzhiyun 		.shift = _shift,			\
47*4882a593Smuzhiyun 		.ops = &mtk_clk_gate_ops_setclr,	\
48*4882a593Smuzhiyun 	}
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static const struct mtk_gate mm_clks[] = {
51*4882a593Smuzhiyun 	/* MM0 */
52*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
53*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
54*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
55*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
56*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
57*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
58*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
59*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
60*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
61*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
62*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
63*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
64*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
65*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
66*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
67*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
68*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
69*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
70*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
71*4882a593Smuzhiyun 	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
72*4882a593Smuzhiyun 	/* MM1 */
73*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
74*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
75*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
76*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
77*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
78*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
79*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
80*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
81*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
82*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
83*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
84*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
85*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
86*4882a593Smuzhiyun 	GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun struct clk_mt8167_mm_driver_data {
90*4882a593Smuzhiyun 	const struct mtk_gate *gates_clk;
91*4882a593Smuzhiyun 	int gates_num;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = {
95*4882a593Smuzhiyun 	.gates_clk = mm_clks,
96*4882a593Smuzhiyun 	.gates_num = ARRAY_SIZE(mm_clks),
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
clk_mt8167_mm_probe(struct platform_device * pdev)99*4882a593Smuzhiyun static int clk_mt8167_mm_probe(struct platform_device *pdev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
102*4882a593Smuzhiyun 	struct device_node *node = dev->parent->of_node;
103*4882a593Smuzhiyun 	const struct clk_mt8167_mm_driver_data *data;
104*4882a593Smuzhiyun 	struct clk_onecell_data *clk_data;
105*4882a593Smuzhiyun 	int ret;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
108*4882a593Smuzhiyun 	if (!clk_data)
109*4882a593Smuzhiyun 		return -ENOMEM;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	data = &mt8167_mmsys_driver_data;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
114*4882a593Smuzhiyun 				     clk_data);
115*4882a593Smuzhiyun 	if (ret)
116*4882a593Smuzhiyun 		return ret;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
119*4882a593Smuzhiyun 	if (ret)
120*4882a593Smuzhiyun 		return ret;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static struct platform_driver clk_mt8173_mm_drv = {
126*4882a593Smuzhiyun 	.driver = {
127*4882a593Smuzhiyun 		.name = "clk-mt8167-mm",
128*4882a593Smuzhiyun 	},
129*4882a593Smuzhiyun 	.probe = clk_mt8167_mm_probe,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun builtin_platform_driver(clk_mt8173_mm_drv);
133