1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt6797-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs vdec0_cg_regs = {
16*4882a593Smuzhiyun .set_ofs = 0x0000,
17*4882a593Smuzhiyun .clr_ofs = 0x0004,
18*4882a593Smuzhiyun .sta_ofs = 0x0000,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct mtk_gate_regs vdec1_cg_regs = {
22*4882a593Smuzhiyun .set_ofs = 0x0008,
23*4882a593Smuzhiyun .clr_ofs = 0x000c,
24*4882a593Smuzhiyun .sta_ofs = 0x0008,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define GATE_VDEC0(_id, _name, _parent, _shift) { \
28*4882a593Smuzhiyun .id = _id, \
29*4882a593Smuzhiyun .name = _name, \
30*4882a593Smuzhiyun .parent_name = _parent, \
31*4882a593Smuzhiyun .regs = &vdec0_cg_regs, \
32*4882a593Smuzhiyun .shift = _shift, \
33*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr_inv, \
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define GATE_VDEC1(_id, _name, _parent, _shift) { \
37*4882a593Smuzhiyun .id = _id, \
38*4882a593Smuzhiyun .name = _name, \
39*4882a593Smuzhiyun .parent_name = _parent, \
40*4882a593Smuzhiyun .regs = &vdec1_cg_regs, \
41*4882a593Smuzhiyun .shift = _shift, \
42*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr_inv, \
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const struct mtk_gate vdec_clks[] = {
46*4882a593Smuzhiyun GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
47*4882a593Smuzhiyun GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
48*4882a593Smuzhiyun GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
49*4882a593Smuzhiyun GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt6797_vdec[] = {
53*4882a593Smuzhiyun { .compatible = "mediatek,mt6797-vdecsys", },
54*4882a593Smuzhiyun {}
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
clk_mt6797_vdec_probe(struct platform_device * pdev)57*4882a593Smuzhiyun static int clk_mt6797_vdec_probe(struct platform_device *pdev)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
60*4882a593Smuzhiyun int r;
61*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
66*4882a593Smuzhiyun clk_data);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
69*4882a593Smuzhiyun if (r)
70*4882a593Smuzhiyun dev_err(&pdev->dev,
71*4882a593Smuzhiyun "could not register clock provider: %s: %d\n",
72*4882a593Smuzhiyun pdev->name, r);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return r;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static struct platform_driver clk_mt6797_vdec_drv = {
78*4882a593Smuzhiyun .probe = clk_mt6797_vdec_probe,
79*4882a593Smuzhiyun .driver = {
80*4882a593Smuzhiyun .name = "clk-mt6797-vdec",
81*4882a593Smuzhiyun .of_match_table = of_match_clk_mt6797_vdec,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun builtin_platform_driver(clk_mt6797_vdec_drv);
86