1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Wendell Lin <wendell.lin@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "clk-mtk.h"
14*4882a593Smuzhiyun #include "clk-gate.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <dt-bindings/clock/mt6779-clk.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static const struct mtk_gate_regs audio0_cg_regs = {
19*4882a593Smuzhiyun .set_ofs = 0x0,
20*4882a593Smuzhiyun .clr_ofs = 0x0,
21*4882a593Smuzhiyun .sta_ofs = 0x0,
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const struct mtk_gate_regs audio1_cg_regs = {
25*4882a593Smuzhiyun .set_ofs = 0x4,
26*4882a593Smuzhiyun .clr_ofs = 0x4,
27*4882a593Smuzhiyun .sta_ofs = 0x4,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define GATE_AUDIO0(_id, _name, _parent, _shift) \
31*4882a593Smuzhiyun GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
32*4882a593Smuzhiyun &mtk_clk_gate_ops_no_setclr)
33*4882a593Smuzhiyun #define GATE_AUDIO1(_id, _name, _parent, _shift) \
34*4882a593Smuzhiyun GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
35*4882a593Smuzhiyun &mtk_clk_gate_ops_no_setclr)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const struct mtk_gate audio_clks[] = {
38*4882a593Smuzhiyun /* AUDIO0 */
39*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
40*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
41*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
42*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
43*4882a593Smuzhiyun "aud_eng2_sel", 18),
44*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
45*4882a593Smuzhiyun "aud_eng1_sel", 19),
46*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
47*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
48*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
49*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
50*4882a593Smuzhiyun "audio_sel", 26),
51*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
52*4882a593Smuzhiyun GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
53*4882a593Smuzhiyun /* AUDIO1 */
54*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
55*4882a593Smuzhiyun "audio_sel", 4),
56*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
57*4882a593Smuzhiyun "audio_sel", 5),
58*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
59*4882a593Smuzhiyun "audio_sel", 6),
60*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
61*4882a593Smuzhiyun "audio_sel", 7),
62*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
63*4882a593Smuzhiyun "audio_sel", 8),
64*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
65*4882a593Smuzhiyun "audio_sel", 12),
66*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
67*4882a593Smuzhiyun "audio_sel", 13),
68*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
69*4882a593Smuzhiyun "audio_sel", 14),
70*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
71*4882a593Smuzhiyun "audio_h_sel", 15),
72*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
73*4882a593Smuzhiyun "audio_h_sel", 16),
74*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
75*4882a593Smuzhiyun "audio_h_sel", 17),
76*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
77*4882a593Smuzhiyun "audio_sel", 20),
78*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
79*4882a593Smuzhiyun "audio_h_sel",
80*4882a593Smuzhiyun 21),
81*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
82*4882a593Smuzhiyun 28),
83*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
84*4882a593Smuzhiyun "audio_sel", 29),
85*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
86*4882a593Smuzhiyun "audio_sel", 30),
87*4882a593Smuzhiyun GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
88*4882a593Smuzhiyun "audio_h_sel", 31),
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt6779_aud[] = {
92*4882a593Smuzhiyun { .compatible = "mediatek,mt6779-audio", },
93*4882a593Smuzhiyun {}
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
clk_mt6779_aud_probe(struct platform_device * pdev)96*4882a593Smuzhiyun static int clk_mt6779_aud_probe(struct platform_device *pdev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
99*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
104*4882a593Smuzhiyun clk_data);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static struct platform_driver clk_mt6779_aud_drv = {
110*4882a593Smuzhiyun .probe = clk_mt6779_aud_probe,
111*4882a593Smuzhiyun .driver = {
112*4882a593Smuzhiyun .name = "clk-mt6779-aud",
113*4882a593Smuzhiyun .of_match_table = of_match_clk_mt6779_aud,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun builtin_platform_driver(clk_mt6779_aud_drv);
118