xref: /OK3568_Linux_fs/kernel/drivers/clk/mediatek/clk-mt2712-vdec.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2017 MediaTek Inc.
4*4882a593Smuzhiyun  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt2712-clk.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun static const struct mtk_gate_regs vdec0_cg_regs = {
16*4882a593Smuzhiyun 	.set_ofs = 0x0,
17*4882a593Smuzhiyun 	.clr_ofs = 0x4,
18*4882a593Smuzhiyun 	.sta_ofs = 0x0,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun static const struct mtk_gate_regs vdec1_cg_regs = {
22*4882a593Smuzhiyun 	.set_ofs = 0x8,
23*4882a593Smuzhiyun 	.clr_ofs = 0xc,
24*4882a593Smuzhiyun 	.sta_ofs = 0x8,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define GATE_VDEC0(_id, _name, _parent, _shift) {	\
28*4882a593Smuzhiyun 		.id = _id,				\
29*4882a593Smuzhiyun 		.name = _name,				\
30*4882a593Smuzhiyun 		.parent_name = _parent,			\
31*4882a593Smuzhiyun 		.regs = &vdec0_cg_regs,			\
32*4882a593Smuzhiyun 		.shift = _shift,			\
33*4882a593Smuzhiyun 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
34*4882a593Smuzhiyun 	}
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define GATE_VDEC1(_id, _name, _parent, _shift) {	\
37*4882a593Smuzhiyun 		.id = _id,				\
38*4882a593Smuzhiyun 		.name = _name,				\
39*4882a593Smuzhiyun 		.parent_name = _parent,			\
40*4882a593Smuzhiyun 		.regs = &vdec1_cg_regs,			\
41*4882a593Smuzhiyun 		.shift = _shift,			\
42*4882a593Smuzhiyun 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
43*4882a593Smuzhiyun 	}
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static const struct mtk_gate vdec_clks[] = {
46*4882a593Smuzhiyun 	/* VDEC0 */
47*4882a593Smuzhiyun 	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
48*4882a593Smuzhiyun 	/* VDEC1 */
49*4882a593Smuzhiyun 	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
50*4882a593Smuzhiyun 	GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
clk_mt2712_vdec_probe(struct platform_device * pdev)53*4882a593Smuzhiyun static int clk_mt2712_vdec_probe(struct platform_device *pdev)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct clk_onecell_data *clk_data;
56*4882a593Smuzhiyun 	int r;
57*4882a593Smuzhiyun 	struct device_node *node = pdev->dev.of_node;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
62*4882a593Smuzhiyun 			clk_data);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	if (r != 0)
67*4882a593Smuzhiyun 		pr_err("%s(): could not register clock provider: %d\n",
68*4882a593Smuzhiyun 			__func__, r);
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	return r;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt2712_vdec[] = {
74*4882a593Smuzhiyun 	{ .compatible = "mediatek,mt2712-vdecsys", },
75*4882a593Smuzhiyun 	{}
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun static struct platform_driver clk_mt2712_vdec_drv = {
79*4882a593Smuzhiyun 	.probe = clk_mt2712_vdec_probe,
80*4882a593Smuzhiyun 	.driver = {
81*4882a593Smuzhiyun 		.name = "clk-mt2712-vdec",
82*4882a593Smuzhiyun 		.of_match_table = of_match_clk_mt2712_vdec,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun builtin_platform_driver(clk_mt2712_vdec_drv);
87