1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc.
4*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __DRV_CLK_GATE_H
8*4882a593Smuzhiyun #define __DRV_CLK_GATE_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct clk;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct mtk_clk_gate {
16*4882a593Smuzhiyun struct clk_hw hw;
17*4882a593Smuzhiyun struct regmap *regmap;
18*4882a593Smuzhiyun int set_ofs;
19*4882a593Smuzhiyun int clr_ofs;
20*4882a593Smuzhiyun int sta_ofs;
21*4882a593Smuzhiyun u8 bit;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
to_mtk_clk_gate(struct clk_hw * hw)24*4882a593Smuzhiyun static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun return container_of(hw, struct mtk_clk_gate, hw);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun extern const struct clk_ops mtk_clk_gate_ops_setclr;
30*4882a593Smuzhiyun extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
31*4882a593Smuzhiyun extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
32*4882a593Smuzhiyun extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct clk *mtk_clk_register_gate(
35*4882a593Smuzhiyun const char *name,
36*4882a593Smuzhiyun const char *parent_name,
37*4882a593Smuzhiyun struct regmap *regmap,
38*4882a593Smuzhiyun int set_ofs,
39*4882a593Smuzhiyun int clr_ofs,
40*4882a593Smuzhiyun int sta_ofs,
41*4882a593Smuzhiyun u8 bit,
42*4882a593Smuzhiyun const struct clk_ops *ops,
43*4882a593Smuzhiyun unsigned long flags,
44*4882a593Smuzhiyun struct device *dev);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
47*4882a593Smuzhiyun _ops, _flags) { \
48*4882a593Smuzhiyun .id = _id, \
49*4882a593Smuzhiyun .name = _name, \
50*4882a593Smuzhiyun .parent_name = _parent, \
51*4882a593Smuzhiyun .regs = _regs, \
52*4882a593Smuzhiyun .shift = _shift, \
53*4882a593Smuzhiyun .ops = _ops, \
54*4882a593Smuzhiyun .flags = _flags, \
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
58*4882a593Smuzhiyun GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #endif /* __DRV_CLK_GATE_H */
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