1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015 Linaro Ltd.
4*4882a593Smuzhiyun * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "clk-mtk.h"
12*4882a593Smuzhiyun #include "clk-cpumux.h"
13*4882a593Smuzhiyun
to_mtk_clk_cpumux(struct clk_hw * _hw)14*4882a593Smuzhiyun static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun return container_of(_hw, struct mtk_clk_cpumux, hw);
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
clk_cpumux_get_parent(struct clk_hw * hw)19*4882a593Smuzhiyun static u8 clk_cpumux_get_parent(struct clk_hw *hw)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
22*4882a593Smuzhiyun unsigned int val;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun regmap_read(mux->regmap, mux->reg, &val);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun val >>= mux->shift;
27*4882a593Smuzhiyun val &= mux->mask;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return val;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
clk_cpumux_set_parent(struct clk_hw * hw,u8 index)32*4882a593Smuzhiyun static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
35*4882a593Smuzhiyun u32 mask, val;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun val = index << mux->shift;
38*4882a593Smuzhiyun mask = mux->mask << mux->shift;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return regmap_update_bits(mux->regmap, mux->reg, mask, val);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const struct clk_ops clk_cpumux_ops = {
44*4882a593Smuzhiyun .get_parent = clk_cpumux_get_parent,
45*4882a593Smuzhiyun .set_parent = clk_cpumux_set_parent,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct clk *
mtk_clk_register_cpumux(const struct mtk_composite * mux,struct regmap * regmap)49*4882a593Smuzhiyun mtk_clk_register_cpumux(const struct mtk_composite *mux,
50*4882a593Smuzhiyun struct regmap *regmap)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct mtk_clk_cpumux *cpumux;
53*4882a593Smuzhiyun struct clk *clk;
54*4882a593Smuzhiyun struct clk_init_data init;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
57*4882a593Smuzhiyun if (!cpumux)
58*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun init.name = mux->name;
61*4882a593Smuzhiyun init.ops = &clk_cpumux_ops;
62*4882a593Smuzhiyun init.parent_names = mux->parent_names;
63*4882a593Smuzhiyun init.num_parents = mux->num_parents;
64*4882a593Smuzhiyun init.flags = mux->flags;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun cpumux->reg = mux->mux_reg;
67*4882a593Smuzhiyun cpumux->shift = mux->mux_shift;
68*4882a593Smuzhiyun cpumux->mask = BIT(mux->mux_width) - 1;
69*4882a593Smuzhiyun cpumux->regmap = regmap;
70*4882a593Smuzhiyun cpumux->hw.init = &init;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun clk = clk_register(NULL, &cpumux->hw);
73*4882a593Smuzhiyun if (IS_ERR(clk))
74*4882a593Smuzhiyun kfree(cpumux);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return clk;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
mtk_clk_register_cpumuxes(struct device_node * node,const struct mtk_composite * clks,int num,struct clk_onecell_data * clk_data)79*4882a593Smuzhiyun int mtk_clk_register_cpumuxes(struct device_node *node,
80*4882a593Smuzhiyun const struct mtk_composite *clks, int num,
81*4882a593Smuzhiyun struct clk_onecell_data *clk_data)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int i;
84*4882a593Smuzhiyun struct clk *clk;
85*4882a593Smuzhiyun struct regmap *regmap;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun regmap = syscon_node_to_regmap(node);
88*4882a593Smuzhiyun if (IS_ERR(regmap)) {
89*4882a593Smuzhiyun pr_err("Cannot find regmap for %pOF: %ld\n", node,
90*4882a593Smuzhiyun PTR_ERR(regmap));
91*4882a593Smuzhiyun return PTR_ERR(regmap);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun for (i = 0; i < num; i++) {
95*4882a593Smuzhiyun const struct mtk_composite *mux = &clks[i];
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun clk = mtk_clk_register_cpumux(mux, regmap);
98*4882a593Smuzhiyun if (IS_ERR(clk)) {
99*4882a593Smuzhiyun pr_err("Failed to register clk %s: %ld\n",
100*4882a593Smuzhiyun mux->name, PTR_ERR(clk));
101*4882a593Smuzhiyun continue;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun clk_data->clks[mux->id] = clk;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
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