1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clkdev.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <loongson1.h>
11*4882a593Smuzhiyun #include "clk.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define OSC (24 * 1000000)
14*4882a593Smuzhiyun #define DIV_APB 1
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static DEFINE_SPINLOCK(_lock);
17*4882a593Smuzhiyun
ls1x_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)18*4882a593Smuzhiyun static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
19*4882a593Smuzhiyun unsigned long parent_rate)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun u32 pll, rate;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun pll = __raw_readl(LS1X_CLK_PLL_FREQ);
24*4882a593Smuzhiyun rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
25*4882a593Smuzhiyun rate *= OSC;
26*4882a593Smuzhiyun rate >>= 2;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return rate;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static const struct clk_ops ls1x_pll_clk_ops = {
32*4882a593Smuzhiyun .recalc_rate = ls1x_pll_recalc_rate,
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct clk_div_table ahb_div_table[] = {
36*4882a593Smuzhiyun [0] = { .val = 0, .div = 2 },
37*4882a593Smuzhiyun [1] = { .val = 1, .div = 4 },
38*4882a593Smuzhiyun [2] = { .val = 2, .div = 3 },
39*4882a593Smuzhiyun [3] = { .val = 3, .div = 3 },
40*4882a593Smuzhiyun [4] = { /* sentinel */ }
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
ls1x_clk_init(void)43*4882a593Smuzhiyun void __init ls1x_clk_init(void)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct clk_hw *hw;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
48*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "osc_clk", NULL);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* clock derived from 24 MHz OSC clk */
51*4882a593Smuzhiyun hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
52*4882a593Smuzhiyun &ls1x_pll_clk_ops, 0);
53*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "pll_clk", NULL);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
56*4882a593Smuzhiyun CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
57*4882a593Smuzhiyun DIV_CPU_SHIFT, DIV_CPU_WIDTH,
58*4882a593Smuzhiyun CLK_DIVIDER_ONE_BASED |
59*4882a593Smuzhiyun CLK_DIVIDER_ROUND_CLOSEST, &_lock);
60*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
61*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
62*4882a593Smuzhiyun 0, 1, 1);
63*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "cpu_clk", NULL);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
66*4882a593Smuzhiyun 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
67*4882a593Smuzhiyun DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
68*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
69*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
70*4882a593Smuzhiyun 0, 1, 1);
71*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "dc_clk", NULL);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
74*4882a593Smuzhiyun 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
75*4882a593Smuzhiyun DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
76*4882a593Smuzhiyun ahb_div_table, &_lock);
77*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
78*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
79*4882a593Smuzhiyun 0, 1, 1);
80*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ahb_clk", NULL);
81*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
82*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "stmmaceth", NULL);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* clock derived from AHB clk */
85*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
86*4882a593Smuzhiyun DIV_APB);
87*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "apb_clk", NULL);
88*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
89*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
90*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
91*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
92*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
93*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
94*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "serial8250", NULL);
95*4882a593Smuzhiyun }
96