1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clkdev.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <loongson1.h>
12*4882a593Smuzhiyun #include "clk.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define OSC (33 * 1000000)
15*4882a593Smuzhiyun #define DIV_APB 2
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static DEFINE_SPINLOCK(_lock);
18*4882a593Smuzhiyun
ls1x_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)19*4882a593Smuzhiyun static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
20*4882a593Smuzhiyun unsigned long parent_rate)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun u32 pll, rate;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun pll = __raw_readl(LS1X_CLK_PLL_FREQ);
25*4882a593Smuzhiyun rate = 12 + (pll & GENMASK(5, 0));
26*4882a593Smuzhiyun rate *= OSC;
27*4882a593Smuzhiyun rate >>= 1;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return rate;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct clk_ops ls1x_pll_clk_ops = {
33*4882a593Smuzhiyun .recalc_rate = ls1x_pll_recalc_rate,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", };
37*4882a593Smuzhiyun static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", };
38*4882a593Smuzhiyun static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", };
39*4882a593Smuzhiyun
ls1x_clk_init(void)40*4882a593Smuzhiyun void __init ls1x_clk_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct clk_hw *hw;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
45*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "osc_clk", NULL);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* clock derived from 33 MHz OSC clk */
48*4882a593Smuzhiyun hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
49*4882a593Smuzhiyun &ls1x_pll_clk_ops, 0);
50*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "pll_clk", NULL);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* clock derived from PLL clk */
53*4882a593Smuzhiyun /* _____
54*4882a593Smuzhiyun * _______________________| |
55*4882a593Smuzhiyun * OSC ___/ | MUX |___ CPU CLK
56*4882a593Smuzhiyun * \___ PLL ___ CPU DIV ___| |
57*4882a593Smuzhiyun * |_____|
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
60*4882a593Smuzhiyun CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
61*4882a593Smuzhiyun DIV_CPU_SHIFT, DIV_CPU_WIDTH,
62*4882a593Smuzhiyun CLK_DIVIDER_ONE_BASED |
63*4882a593Smuzhiyun CLK_DIVIDER_ROUND_CLOSEST, &_lock);
64*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
65*4882a593Smuzhiyun hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
66*4882a593Smuzhiyun ARRAY_SIZE(cpu_parents),
67*4882a593Smuzhiyun CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
68*4882a593Smuzhiyun BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
69*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "cpu_clk", NULL);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* _____
72*4882a593Smuzhiyun * _______________________| |
73*4882a593Smuzhiyun * OSC ___/ | MUX |___ DC CLK
74*4882a593Smuzhiyun * \___ PLL ___ DC DIV ___| |
75*4882a593Smuzhiyun * |_____|
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
78*4882a593Smuzhiyun 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
79*4882a593Smuzhiyun DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
80*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
81*4882a593Smuzhiyun hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
82*4882a593Smuzhiyun ARRAY_SIZE(dc_parents),
83*4882a593Smuzhiyun CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
84*4882a593Smuzhiyun BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
85*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "dc_clk", NULL);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* _____
88*4882a593Smuzhiyun * _______________________| |
89*4882a593Smuzhiyun * OSC ___/ | MUX |___ DDR CLK
90*4882a593Smuzhiyun * \___ PLL ___ DDR DIV ___| |
91*4882a593Smuzhiyun * |_____|
92*4882a593Smuzhiyun */
93*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
94*4882a593Smuzhiyun 0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
95*4882a593Smuzhiyun DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
96*4882a593Smuzhiyun &_lock);
97*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
98*4882a593Smuzhiyun hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
99*4882a593Smuzhiyun ARRAY_SIZE(ahb_parents),
100*4882a593Smuzhiyun CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
101*4882a593Smuzhiyun BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
102*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ahb_clk", NULL);
103*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
104*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "stmmaceth", NULL);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* clock derived from AHB clk */
107*4882a593Smuzhiyun /* APB clk is always half of the AHB clk */
108*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
109*4882a593Smuzhiyun DIV_APB);
110*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "apb_clk", NULL);
111*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
112*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
113*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
114*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
115*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
116*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
117*4882a593Smuzhiyun clk_hw_register_clkdev(hw, "serial8250", NULL);
118*4882a593Smuzhiyun }
119