xref: /OK3568_Linux_fs/kernel/drivers/clk/keystone/sci-clk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * SCI Clock driver for keystone based devices
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
5*4882a593Smuzhiyun  *	Tero Kristo <t-kristo@ti.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
8*4882a593Smuzhiyun  * it under the terms of the GNU General Public License version 2 as
9*4882a593Smuzhiyun  * published by the Free Software Foundation.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
13*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14*4882a593Smuzhiyun  * GNU General Public License for more details.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun #include <linux/clk-provider.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/of_address.h>
21*4882a593Smuzhiyun #include <linux/of_device.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/slab.h>
24*4882a593Smuzhiyun #include <linux/soc/ti/ti_sci_protocol.h>
25*4882a593Smuzhiyun #include <linux/bsearch.h>
26*4882a593Smuzhiyun #include <linux/list_sort.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define SCI_CLK_SSC_ENABLE		BIT(0)
29*4882a593Smuzhiyun #define SCI_CLK_ALLOW_FREQ_CHANGE	BIT(1)
30*4882a593Smuzhiyun #define SCI_CLK_INPUT_TERMINATION	BIT(2)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /**
33*4882a593Smuzhiyun  * struct sci_clk_provider - TI SCI clock provider representation
34*4882a593Smuzhiyun  * @sci: Handle to the System Control Interface protocol handler
35*4882a593Smuzhiyun  * @ops: Pointer to the SCI ops to be used by the clocks
36*4882a593Smuzhiyun  * @dev: Device pointer for the clock provider
37*4882a593Smuzhiyun  * @clocks: Clocks array for this device
38*4882a593Smuzhiyun  * @num_clocks: Total number of clocks for this provider
39*4882a593Smuzhiyun  */
40*4882a593Smuzhiyun struct sci_clk_provider {
41*4882a593Smuzhiyun 	const struct ti_sci_handle *sci;
42*4882a593Smuzhiyun 	const struct ti_sci_clk_ops *ops;
43*4882a593Smuzhiyun 	struct device *dev;
44*4882a593Smuzhiyun 	struct sci_clk **clocks;
45*4882a593Smuzhiyun 	int num_clocks;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun  * struct sci_clk - TI SCI clock representation
50*4882a593Smuzhiyun  * @hw:		 Hardware clock cookie for common clock framework
51*4882a593Smuzhiyun  * @dev_id:	 Device index
52*4882a593Smuzhiyun  * @clk_id:	 Clock index
53*4882a593Smuzhiyun  * @num_parents: Number of parents for this clock
54*4882a593Smuzhiyun  * @provider:	 Master clock provider
55*4882a593Smuzhiyun  * @flags:	 Flags for the clock
56*4882a593Smuzhiyun  * @node:	 Link for handling clocks probed via DT
57*4882a593Smuzhiyun  * @cached_req:	 Cached requested freq for determine rate calls
58*4882a593Smuzhiyun  * @cached_res:	 Cached result freq for determine rate calls
59*4882a593Smuzhiyun  */
60*4882a593Smuzhiyun struct sci_clk {
61*4882a593Smuzhiyun 	struct clk_hw hw;
62*4882a593Smuzhiyun 	u16 dev_id;
63*4882a593Smuzhiyun 	u32 clk_id;
64*4882a593Smuzhiyun 	u32 num_parents;
65*4882a593Smuzhiyun 	struct sci_clk_provider *provider;
66*4882a593Smuzhiyun 	u8 flags;
67*4882a593Smuzhiyun 	struct list_head node;
68*4882a593Smuzhiyun 	unsigned long cached_req;
69*4882a593Smuzhiyun 	unsigned long cached_res;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /**
75*4882a593Smuzhiyun  * sci_clk_prepare - Prepare (enable) a TI SCI clock
76*4882a593Smuzhiyun  * @hw: clock to prepare
77*4882a593Smuzhiyun  *
78*4882a593Smuzhiyun  * Prepares a clock to be actively used. Returns the SCI protocol status.
79*4882a593Smuzhiyun  */
sci_clk_prepare(struct clk_hw * hw)80*4882a593Smuzhiyun static int sci_clk_prepare(struct clk_hw *hw)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
83*4882a593Smuzhiyun 	bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE;
84*4882a593Smuzhiyun 	bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE;
85*4882a593Smuzhiyun 	bool input_termination = clk->flags & SCI_CLK_INPUT_TERMINATION;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return clk->provider->ops->get_clock(clk->provider->sci, clk->dev_id,
88*4882a593Smuzhiyun 					     clk->clk_id, enable_ssc,
89*4882a593Smuzhiyun 					     allow_freq_change,
90*4882a593Smuzhiyun 					     input_termination);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /**
94*4882a593Smuzhiyun  * sci_clk_unprepare - Un-prepares (disables) a TI SCI clock
95*4882a593Smuzhiyun  * @hw: clock to unprepare
96*4882a593Smuzhiyun  *
97*4882a593Smuzhiyun  * Un-prepares a clock from active state.
98*4882a593Smuzhiyun  */
sci_clk_unprepare(struct clk_hw * hw)99*4882a593Smuzhiyun static void sci_clk_unprepare(struct clk_hw *hw)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
102*4882a593Smuzhiyun 	int ret;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = clk->provider->ops->put_clock(clk->provider->sci, clk->dev_id,
105*4882a593Smuzhiyun 					    clk->clk_id);
106*4882a593Smuzhiyun 	if (ret)
107*4882a593Smuzhiyun 		dev_err(clk->provider->dev,
108*4882a593Smuzhiyun 			"unprepare failed for dev=%d, clk=%d, ret=%d\n",
109*4882a593Smuzhiyun 			clk->dev_id, clk->clk_id, ret);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /**
113*4882a593Smuzhiyun  * sci_clk_is_prepared - Check if a TI SCI clock is prepared or not
114*4882a593Smuzhiyun  * @hw: clock to check status for
115*4882a593Smuzhiyun  *
116*4882a593Smuzhiyun  * Checks if a clock is prepared (enabled) in hardware. Returns non-zero
117*4882a593Smuzhiyun  * value if clock is enabled, zero otherwise.
118*4882a593Smuzhiyun  */
sci_clk_is_prepared(struct clk_hw * hw)119*4882a593Smuzhiyun static int sci_clk_is_prepared(struct clk_hw *hw)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
122*4882a593Smuzhiyun 	bool req_state, current_state;
123*4882a593Smuzhiyun 	int ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	ret = clk->provider->ops->is_on(clk->provider->sci, clk->dev_id,
126*4882a593Smuzhiyun 					clk->clk_id, &req_state,
127*4882a593Smuzhiyun 					&current_state);
128*4882a593Smuzhiyun 	if (ret) {
129*4882a593Smuzhiyun 		dev_err(clk->provider->dev,
130*4882a593Smuzhiyun 			"is_prepared failed for dev=%d, clk=%d, ret=%d\n",
131*4882a593Smuzhiyun 			clk->dev_id, clk->clk_id, ret);
132*4882a593Smuzhiyun 		return 0;
133*4882a593Smuzhiyun 	}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	return req_state;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /**
139*4882a593Smuzhiyun  * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
140*4882a593Smuzhiyun  * @hw: clock to get rate for
141*4882a593Smuzhiyun  * @parent_rate: parent rate provided by common clock framework, not used
142*4882a593Smuzhiyun  *
143*4882a593Smuzhiyun  * Gets the current clock rate of a TI SCI clock. Returns the current
144*4882a593Smuzhiyun  * clock rate, or zero in failure.
145*4882a593Smuzhiyun  */
sci_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)146*4882a593Smuzhiyun static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
147*4882a593Smuzhiyun 					 unsigned long parent_rate)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
150*4882a593Smuzhiyun 	u64 freq;
151*4882a593Smuzhiyun 	int ret;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
154*4882a593Smuzhiyun 					   clk->clk_id, &freq);
155*4882a593Smuzhiyun 	if (ret) {
156*4882a593Smuzhiyun 		dev_err(clk->provider->dev,
157*4882a593Smuzhiyun 			"recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
158*4882a593Smuzhiyun 			clk->dev_id, clk->clk_id, ret);
159*4882a593Smuzhiyun 		return 0;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return freq;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /**
166*4882a593Smuzhiyun  * sci_clk_determine_rate - Determines a clock rate a clock can be set to
167*4882a593Smuzhiyun  * @hw: clock to change rate for
168*4882a593Smuzhiyun  * @req: requested rate configuration for the clock
169*4882a593Smuzhiyun  *
170*4882a593Smuzhiyun  * Determines a suitable clock rate and parent for a TI SCI clock.
171*4882a593Smuzhiyun  * The parent handling is un-used, as generally the parent clock rates
172*4882a593Smuzhiyun  * are not known by the kernel; instead these are internally handled
173*4882a593Smuzhiyun  * by the firmware. Returns 0 on success, negative error value on failure.
174*4882a593Smuzhiyun  */
sci_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)175*4882a593Smuzhiyun static int sci_clk_determine_rate(struct clk_hw *hw,
176*4882a593Smuzhiyun 				  struct clk_rate_request *req)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
179*4882a593Smuzhiyun 	int ret;
180*4882a593Smuzhiyun 	u64 new_rate;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	if (clk->cached_req && clk->cached_req == req->rate) {
183*4882a593Smuzhiyun 		req->rate = clk->cached_res;
184*4882a593Smuzhiyun 		return 0;
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
188*4882a593Smuzhiyun 						      clk->dev_id,
189*4882a593Smuzhiyun 						      clk->clk_id,
190*4882a593Smuzhiyun 						      req->min_rate,
191*4882a593Smuzhiyun 						      req->rate,
192*4882a593Smuzhiyun 						      req->max_rate,
193*4882a593Smuzhiyun 						      &new_rate);
194*4882a593Smuzhiyun 	if (ret) {
195*4882a593Smuzhiyun 		dev_err(clk->provider->dev,
196*4882a593Smuzhiyun 			"determine-rate failed for dev=%d, clk=%d, ret=%d\n",
197*4882a593Smuzhiyun 			clk->dev_id, clk->clk_id, ret);
198*4882a593Smuzhiyun 		return ret;
199*4882a593Smuzhiyun 	}
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	clk->cached_req = req->rate;
202*4882a593Smuzhiyun 	clk->cached_res = new_rate;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	req->rate = new_rate;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	return 0;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun /**
210*4882a593Smuzhiyun  * sci_clk_set_rate - Set rate for a TI SCI clock
211*4882a593Smuzhiyun  * @hw: clock to change rate for
212*4882a593Smuzhiyun  * @rate: target rate for the clock
213*4882a593Smuzhiyun  * @parent_rate: rate of the clock parent, not used for TI SCI clocks
214*4882a593Smuzhiyun  *
215*4882a593Smuzhiyun  * Sets a clock frequency for a TI SCI clock. Returns the TI SCI
216*4882a593Smuzhiyun  * protocol status.
217*4882a593Smuzhiyun  */
sci_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)218*4882a593Smuzhiyun static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
219*4882a593Smuzhiyun 			    unsigned long parent_rate)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
224*4882a593Smuzhiyun 					    clk->clk_id, rate / 10 * 9, rate,
225*4882a593Smuzhiyun 					    rate / 10 * 11);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /**
229*4882a593Smuzhiyun  * sci_clk_get_parent - Get the current parent of a TI SCI clock
230*4882a593Smuzhiyun  * @hw: clock to get parent for
231*4882a593Smuzhiyun  *
232*4882a593Smuzhiyun  * Returns the index of the currently selected parent for a TI SCI clock.
233*4882a593Smuzhiyun  */
sci_clk_get_parent(struct clk_hw * hw)234*4882a593Smuzhiyun static u8 sci_clk_get_parent(struct clk_hw *hw)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
237*4882a593Smuzhiyun 	u32 parent_id = 0;
238*4882a593Smuzhiyun 	int ret;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	ret = clk->provider->ops->get_parent(clk->provider->sci, clk->dev_id,
241*4882a593Smuzhiyun 					     clk->clk_id, (void *)&parent_id);
242*4882a593Smuzhiyun 	if (ret) {
243*4882a593Smuzhiyun 		dev_err(clk->provider->dev,
244*4882a593Smuzhiyun 			"get-parent failed for dev=%d, clk=%d, ret=%d\n",
245*4882a593Smuzhiyun 			clk->dev_id, clk->clk_id, ret);
246*4882a593Smuzhiyun 		return 0;
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	parent_id = parent_id - clk->clk_id - 1;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	return (u8)parent_id;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /**
255*4882a593Smuzhiyun  * sci_clk_set_parent - Set the parent of a TI SCI clock
256*4882a593Smuzhiyun  * @hw: clock to set parent for
257*4882a593Smuzhiyun  * @index: new parent index for the clock
258*4882a593Smuzhiyun  *
259*4882a593Smuzhiyun  * Sets the parent of a TI SCI clock. Return TI SCI protocol status.
260*4882a593Smuzhiyun  */
sci_clk_set_parent(struct clk_hw * hw,u8 index)261*4882a593Smuzhiyun static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	struct sci_clk *clk = to_sci_clk(hw);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	clk->cached_req = 0;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
268*4882a593Smuzhiyun 					      clk->clk_id,
269*4882a593Smuzhiyun 					      index + 1 + clk->clk_id);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static const struct clk_ops sci_clk_ops = {
273*4882a593Smuzhiyun 	.prepare = sci_clk_prepare,
274*4882a593Smuzhiyun 	.unprepare = sci_clk_unprepare,
275*4882a593Smuzhiyun 	.is_prepared = sci_clk_is_prepared,
276*4882a593Smuzhiyun 	.recalc_rate = sci_clk_recalc_rate,
277*4882a593Smuzhiyun 	.determine_rate = sci_clk_determine_rate,
278*4882a593Smuzhiyun 	.set_rate = sci_clk_set_rate,
279*4882a593Smuzhiyun 	.get_parent = sci_clk_get_parent,
280*4882a593Smuzhiyun 	.set_parent = sci_clk_set_parent,
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /**
284*4882a593Smuzhiyun  * _sci_clk_get - Gets a handle for an SCI clock
285*4882a593Smuzhiyun  * @provider: Handle to SCI clock provider
286*4882a593Smuzhiyun  * @sci_clk: Handle to the SCI clock to populate
287*4882a593Smuzhiyun  *
288*4882a593Smuzhiyun  * Gets a handle to an existing TI SCI hw clock, or builds a new clock
289*4882a593Smuzhiyun  * entry and registers it with the common clock framework. Called from
290*4882a593Smuzhiyun  * the common clock framework, when a corresponding of_clk_get call is
291*4882a593Smuzhiyun  * executed, or recursively from itself when parsing parent clocks.
292*4882a593Smuzhiyun  * Returns 0 on success, negative error code on failure.
293*4882a593Smuzhiyun  */
_sci_clk_build(struct sci_clk_provider * provider,struct sci_clk * sci_clk)294*4882a593Smuzhiyun static int _sci_clk_build(struct sci_clk_provider *provider,
295*4882a593Smuzhiyun 			  struct sci_clk *sci_clk)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	struct clk_init_data init = { NULL };
298*4882a593Smuzhiyun 	char *name = NULL;
299*4882a593Smuzhiyun 	char **parent_names = NULL;
300*4882a593Smuzhiyun 	int i;
301*4882a593Smuzhiyun 	int ret = 0;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	name = kasprintf(GFP_KERNEL, "clk:%d:%d", sci_clk->dev_id,
304*4882a593Smuzhiyun 			 sci_clk->clk_id);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	init.name = name;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/*
309*4882a593Smuzhiyun 	 * From kernel point of view, we only care about a clocks parents,
310*4882a593Smuzhiyun 	 * if it has more than 1 possible parent. In this case, it is going
311*4882a593Smuzhiyun 	 * to have mux functionality. Otherwise it is going to act as a root
312*4882a593Smuzhiyun 	 * clock.
313*4882a593Smuzhiyun 	 */
314*4882a593Smuzhiyun 	if (sci_clk->num_parents < 2)
315*4882a593Smuzhiyun 		sci_clk->num_parents = 0;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	if (sci_clk->num_parents) {
318*4882a593Smuzhiyun 		parent_names = kcalloc(sci_clk->num_parents, sizeof(char *),
319*4882a593Smuzhiyun 				       GFP_KERNEL);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 		if (!parent_names) {
322*4882a593Smuzhiyun 			ret = -ENOMEM;
323*4882a593Smuzhiyun 			goto err;
324*4882a593Smuzhiyun 		}
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 		for (i = 0; i < sci_clk->num_parents; i++) {
327*4882a593Smuzhiyun 			char *parent_name;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 			parent_name = kasprintf(GFP_KERNEL, "clk:%d:%d",
330*4882a593Smuzhiyun 						sci_clk->dev_id,
331*4882a593Smuzhiyun 						sci_clk->clk_id + 1 + i);
332*4882a593Smuzhiyun 			if (!parent_name) {
333*4882a593Smuzhiyun 				ret = -ENOMEM;
334*4882a593Smuzhiyun 				goto err;
335*4882a593Smuzhiyun 			}
336*4882a593Smuzhiyun 			parent_names[i] = parent_name;
337*4882a593Smuzhiyun 		}
338*4882a593Smuzhiyun 		init.parent_names = (void *)parent_names;
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	init.ops = &sci_clk_ops;
342*4882a593Smuzhiyun 	init.num_parents = sci_clk->num_parents;
343*4882a593Smuzhiyun 	sci_clk->hw.init = &init;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
346*4882a593Smuzhiyun 	if (ret)
347*4882a593Smuzhiyun 		dev_err(provider->dev, "failed clk register with %d\n", ret);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun err:
350*4882a593Smuzhiyun 	if (parent_names) {
351*4882a593Smuzhiyun 		for (i = 0; i < sci_clk->num_parents; i++)
352*4882a593Smuzhiyun 			kfree(parent_names[i]);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 		kfree(parent_names);
355*4882a593Smuzhiyun 	}
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	kfree(name);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	return ret;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun 
_cmp_sci_clk(const void * a,const void * b)362*4882a593Smuzhiyun static int _cmp_sci_clk(const void *a, const void *b)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	const struct sci_clk *ca = a;
365*4882a593Smuzhiyun 	const struct sci_clk *cb = *(struct sci_clk **)b;
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	if (ca->dev_id == cb->dev_id && ca->clk_id == cb->clk_id)
368*4882a593Smuzhiyun 		return 0;
369*4882a593Smuzhiyun 	if (ca->dev_id > cb->dev_id ||
370*4882a593Smuzhiyun 	    (ca->dev_id == cb->dev_id && ca->clk_id > cb->clk_id))
371*4882a593Smuzhiyun 		return 1;
372*4882a593Smuzhiyun 	return -1;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun /**
376*4882a593Smuzhiyun  * sci_clk_get - Xlate function for getting clock handles
377*4882a593Smuzhiyun  * @clkspec: device tree clock specifier
378*4882a593Smuzhiyun  * @data: pointer to the clock provider
379*4882a593Smuzhiyun  *
380*4882a593Smuzhiyun  * Xlate function for retrieving clock TI SCI hw clock handles based on
381*4882a593Smuzhiyun  * device tree clock specifier. Called from the common clock framework,
382*4882a593Smuzhiyun  * when a corresponding of_clk_get call is executed. Returns a pointer
383*4882a593Smuzhiyun  * to the TI SCI hw clock struct, or ERR_PTR value in failure.
384*4882a593Smuzhiyun  */
sci_clk_get(struct of_phandle_args * clkspec,void * data)385*4882a593Smuzhiyun static struct clk_hw *sci_clk_get(struct of_phandle_args *clkspec, void *data)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct sci_clk_provider *provider = data;
388*4882a593Smuzhiyun 	struct sci_clk **clk;
389*4882a593Smuzhiyun 	struct sci_clk key;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	if (clkspec->args_count != 2)
392*4882a593Smuzhiyun 		return ERR_PTR(-EINVAL);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	key.dev_id = clkspec->args[0];
395*4882a593Smuzhiyun 	key.clk_id = clkspec->args[1];
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	clk = bsearch(&key, provider->clocks, provider->num_clocks,
398*4882a593Smuzhiyun 		      sizeof(clk), _cmp_sci_clk);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	if (!clk)
401*4882a593Smuzhiyun 		return ERR_PTR(-ENODEV);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	return &(*clk)->hw;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun 
ti_sci_init_clocks(struct sci_clk_provider * p)406*4882a593Smuzhiyun static int ti_sci_init_clocks(struct sci_clk_provider *p)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	int i;
409*4882a593Smuzhiyun 	int ret;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	for (i = 0; i < p->num_clocks; i++) {
412*4882a593Smuzhiyun 		ret = _sci_clk_build(p, p->clocks[i]);
413*4882a593Smuzhiyun 		if (ret)
414*4882a593Smuzhiyun 			return ret;
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	return 0;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun static const struct of_device_id ti_sci_clk_of_match[] = {
421*4882a593Smuzhiyun 	{ .compatible = "ti,k2g-sci-clk" },
422*4882a593Smuzhiyun 	{ /* Sentinel */ },
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ti_sci_clk_of_match);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun #ifdef CONFIG_TI_SCI_CLK_PROBE_FROM_FW
ti_sci_scan_clocks_from_fw(struct sci_clk_provider * provider)427*4882a593Smuzhiyun static int ti_sci_scan_clocks_from_fw(struct sci_clk_provider *provider)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun 	int ret;
430*4882a593Smuzhiyun 	int num_clks = 0;
431*4882a593Smuzhiyun 	struct sci_clk **clks = NULL;
432*4882a593Smuzhiyun 	struct sci_clk **tmp_clks;
433*4882a593Smuzhiyun 	struct sci_clk *sci_clk;
434*4882a593Smuzhiyun 	int max_clks = 0;
435*4882a593Smuzhiyun 	int clk_id = 0;
436*4882a593Smuzhiyun 	int dev_id = 0;
437*4882a593Smuzhiyun 	u32 num_parents = 0;
438*4882a593Smuzhiyun 	int gap_size = 0;
439*4882a593Smuzhiyun 	struct device *dev = provider->dev;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	while (1) {
442*4882a593Smuzhiyun 		ret = provider->ops->get_num_parents(provider->sci, dev_id,
443*4882a593Smuzhiyun 						     clk_id,
444*4882a593Smuzhiyun 						     (void *)&num_parents);
445*4882a593Smuzhiyun 		if (ret) {
446*4882a593Smuzhiyun 			gap_size++;
447*4882a593Smuzhiyun 			if (!clk_id) {
448*4882a593Smuzhiyun 				if (gap_size >= 5)
449*4882a593Smuzhiyun 					break;
450*4882a593Smuzhiyun 				dev_id++;
451*4882a593Smuzhiyun 			} else {
452*4882a593Smuzhiyun 				if (gap_size >= 2) {
453*4882a593Smuzhiyun 					dev_id++;
454*4882a593Smuzhiyun 					clk_id = 0;
455*4882a593Smuzhiyun 					gap_size = 0;
456*4882a593Smuzhiyun 				} else {
457*4882a593Smuzhiyun 					clk_id++;
458*4882a593Smuzhiyun 				}
459*4882a593Smuzhiyun 			}
460*4882a593Smuzhiyun 			continue;
461*4882a593Smuzhiyun 		}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 		gap_size = 0;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 		if (num_clks == max_clks) {
466*4882a593Smuzhiyun 			tmp_clks = devm_kmalloc_array(dev, max_clks + 64,
467*4882a593Smuzhiyun 						      sizeof(sci_clk),
468*4882a593Smuzhiyun 						      GFP_KERNEL);
469*4882a593Smuzhiyun 			memcpy(tmp_clks, clks, max_clks * sizeof(sci_clk));
470*4882a593Smuzhiyun 			if (max_clks)
471*4882a593Smuzhiyun 				devm_kfree(dev, clks);
472*4882a593Smuzhiyun 			max_clks += 64;
473*4882a593Smuzhiyun 			clks = tmp_clks;
474*4882a593Smuzhiyun 		}
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 		sci_clk = devm_kzalloc(dev, sizeof(*sci_clk), GFP_KERNEL);
477*4882a593Smuzhiyun 		if (!sci_clk)
478*4882a593Smuzhiyun 			return -ENOMEM;
479*4882a593Smuzhiyun 		sci_clk->dev_id = dev_id;
480*4882a593Smuzhiyun 		sci_clk->clk_id = clk_id;
481*4882a593Smuzhiyun 		sci_clk->provider = provider;
482*4882a593Smuzhiyun 		sci_clk->num_parents = num_parents;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 		clks[num_clks] = sci_clk;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 		clk_id++;
487*4882a593Smuzhiyun 		num_clks++;
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	provider->clocks = devm_kmalloc_array(dev, num_clks, sizeof(sci_clk),
491*4882a593Smuzhiyun 					      GFP_KERNEL);
492*4882a593Smuzhiyun 	if (!provider->clocks)
493*4882a593Smuzhiyun 		return -ENOMEM;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	memcpy(provider->clocks, clks, num_clks * sizeof(sci_clk));
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	provider->num_clocks = num_clks;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	devm_kfree(dev, clks);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	return 0;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun #else
505*4882a593Smuzhiyun 
_cmp_sci_clk_list(void * priv,struct list_head * a,struct list_head * b)506*4882a593Smuzhiyun static int _cmp_sci_clk_list(void *priv, struct list_head *a,
507*4882a593Smuzhiyun 			     struct list_head *b)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	struct sci_clk *ca = container_of(a, struct sci_clk, node);
510*4882a593Smuzhiyun 	struct sci_clk *cb = container_of(b, struct sci_clk, node);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	return _cmp_sci_clk(ca, &cb);
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun 
ti_sci_scan_clocks_from_dt(struct sci_clk_provider * provider)515*4882a593Smuzhiyun static int ti_sci_scan_clocks_from_dt(struct sci_clk_provider *provider)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun 	struct device *dev = provider->dev;
518*4882a593Smuzhiyun 	struct device_node *np = NULL;
519*4882a593Smuzhiyun 	int ret;
520*4882a593Smuzhiyun 	int index;
521*4882a593Smuzhiyun 	struct of_phandle_args args;
522*4882a593Smuzhiyun 	struct list_head clks;
523*4882a593Smuzhiyun 	struct sci_clk *sci_clk, *prev;
524*4882a593Smuzhiyun 	int num_clks = 0;
525*4882a593Smuzhiyun 	int num_parents;
526*4882a593Smuzhiyun 	int clk_id;
527*4882a593Smuzhiyun 	const char * const clk_names[] = {
528*4882a593Smuzhiyun 		"clocks", "assigned-clocks", "assigned-clock-parents", NULL
529*4882a593Smuzhiyun 	};
530*4882a593Smuzhiyun 	const char * const *clk_name;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	INIT_LIST_HEAD(&clks);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	clk_name = clk_names;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	while (*clk_name) {
537*4882a593Smuzhiyun 		np = of_find_node_with_property(np, *clk_name);
538*4882a593Smuzhiyun 		if (!np) {
539*4882a593Smuzhiyun 			clk_name++;
540*4882a593Smuzhiyun 			continue;
541*4882a593Smuzhiyun 		}
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 		if (!of_device_is_available(np))
544*4882a593Smuzhiyun 			continue;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 		index = 0;
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 		do {
549*4882a593Smuzhiyun 			ret = of_parse_phandle_with_args(np, *clk_name,
550*4882a593Smuzhiyun 							 "#clock-cells", index,
551*4882a593Smuzhiyun 							 &args);
552*4882a593Smuzhiyun 			if (ret)
553*4882a593Smuzhiyun 				break;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 			if (args.args_count == 2 && args.np == dev->of_node) {
556*4882a593Smuzhiyun 				sci_clk = devm_kzalloc(dev, sizeof(*sci_clk),
557*4882a593Smuzhiyun 						       GFP_KERNEL);
558*4882a593Smuzhiyun 				if (!sci_clk)
559*4882a593Smuzhiyun 					return -ENOMEM;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 				sci_clk->dev_id = args.args[0];
562*4882a593Smuzhiyun 				sci_clk->clk_id = args.args[1];
563*4882a593Smuzhiyun 				sci_clk->provider = provider;
564*4882a593Smuzhiyun 				provider->ops->get_num_parents(provider->sci,
565*4882a593Smuzhiyun 							       sci_clk->dev_id,
566*4882a593Smuzhiyun 							       sci_clk->clk_id,
567*4882a593Smuzhiyun 							       (void *)&sci_clk->num_parents);
568*4882a593Smuzhiyun 				list_add_tail(&sci_clk->node, &clks);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 				num_clks++;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 				num_parents = sci_clk->num_parents;
573*4882a593Smuzhiyun 				if (num_parents == 1)
574*4882a593Smuzhiyun 					num_parents = 0;
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 				/*
577*4882a593Smuzhiyun 				 * Linux kernel has inherent limitation
578*4882a593Smuzhiyun 				 * of 255 clock parents at the moment.
579*4882a593Smuzhiyun 				 * Right now, it is not expected that
580*4882a593Smuzhiyun 				 * any mux clock from sci-clk driver
581*4882a593Smuzhiyun 				 * would exceed that limit either, but
582*4882a593Smuzhiyun 				 * the ABI basically provides that
583*4882a593Smuzhiyun 				 * possibility. Print out a warning if
584*4882a593Smuzhiyun 				 * this happens for any clock.
585*4882a593Smuzhiyun 				 */
586*4882a593Smuzhiyun 				if (num_parents >= 255) {
587*4882a593Smuzhiyun 					dev_warn(dev, "too many parents for dev=%d, clk=%d (%d), cropping to 255.\n",
588*4882a593Smuzhiyun 						 sci_clk->dev_id,
589*4882a593Smuzhiyun 						 sci_clk->clk_id, num_parents);
590*4882a593Smuzhiyun 					num_parents = 255;
591*4882a593Smuzhiyun 				}
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 				clk_id = args.args[1] + 1;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 				while (num_parents--) {
596*4882a593Smuzhiyun 					sci_clk = devm_kzalloc(dev,
597*4882a593Smuzhiyun 							       sizeof(*sci_clk),
598*4882a593Smuzhiyun 							       GFP_KERNEL);
599*4882a593Smuzhiyun 					if (!sci_clk)
600*4882a593Smuzhiyun 						return -ENOMEM;
601*4882a593Smuzhiyun 					sci_clk->dev_id = args.args[0];
602*4882a593Smuzhiyun 					sci_clk->clk_id = clk_id++;
603*4882a593Smuzhiyun 					sci_clk->provider = provider;
604*4882a593Smuzhiyun 					list_add_tail(&sci_clk->node, &clks);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 					num_clks++;
607*4882a593Smuzhiyun 				}
608*4882a593Smuzhiyun 			}
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 			index++;
611*4882a593Smuzhiyun 		} while (args.np);
612*4882a593Smuzhiyun 	}
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	list_sort(NULL, &clks, _cmp_sci_clk_list);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	provider->clocks = devm_kmalloc_array(dev, num_clks, sizeof(sci_clk),
617*4882a593Smuzhiyun 					      GFP_KERNEL);
618*4882a593Smuzhiyun 	if (!provider->clocks)
619*4882a593Smuzhiyun 		return -ENOMEM;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	num_clks = 0;
622*4882a593Smuzhiyun 	prev = NULL;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	list_for_each_entry(sci_clk, &clks, node) {
625*4882a593Smuzhiyun 		if (prev && prev->dev_id == sci_clk->dev_id &&
626*4882a593Smuzhiyun 		    prev->clk_id == sci_clk->clk_id)
627*4882a593Smuzhiyun 			continue;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 		provider->clocks[num_clks++] = sci_clk;
630*4882a593Smuzhiyun 		prev = sci_clk;
631*4882a593Smuzhiyun 	}
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	provider->num_clocks = num_clks;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	return 0;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun #endif
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun /**
640*4882a593Smuzhiyun  * ti_sci_clk_probe - Probe function for the TI SCI clock driver
641*4882a593Smuzhiyun  * @pdev: platform device pointer to be probed
642*4882a593Smuzhiyun  *
643*4882a593Smuzhiyun  * Probes the TI SCI clock device. Allocates a new clock provider
644*4882a593Smuzhiyun  * and registers this to the common clock framework. Also applies
645*4882a593Smuzhiyun  * any required flags to the identified clocks via clock lists
646*4882a593Smuzhiyun  * supplied from DT. Returns 0 for success, negative error value
647*4882a593Smuzhiyun  * for failure.
648*4882a593Smuzhiyun  */
ti_sci_clk_probe(struct platform_device * pdev)649*4882a593Smuzhiyun static int ti_sci_clk_probe(struct platform_device *pdev)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
652*4882a593Smuzhiyun 	struct device_node *np = dev->of_node;
653*4882a593Smuzhiyun 	struct sci_clk_provider *provider;
654*4882a593Smuzhiyun 	const struct ti_sci_handle *handle;
655*4882a593Smuzhiyun 	int ret;
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun 	handle = devm_ti_sci_get_handle(dev);
658*4882a593Smuzhiyun 	if (IS_ERR(handle))
659*4882a593Smuzhiyun 		return PTR_ERR(handle);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
662*4882a593Smuzhiyun 	if (!provider)
663*4882a593Smuzhiyun 		return -ENOMEM;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	provider->sci = handle;
666*4882a593Smuzhiyun 	provider->ops = &handle->ops.clk_ops;
667*4882a593Smuzhiyun 	provider->dev = dev;
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun #ifdef CONFIG_TI_SCI_CLK_PROBE_FROM_FW
670*4882a593Smuzhiyun 	ret = ti_sci_scan_clocks_from_fw(provider);
671*4882a593Smuzhiyun 	if (ret) {
672*4882a593Smuzhiyun 		dev_err(dev, "scan clocks from FW failed: %d\n", ret);
673*4882a593Smuzhiyun 		return ret;
674*4882a593Smuzhiyun 	}
675*4882a593Smuzhiyun #else
676*4882a593Smuzhiyun 	ret = ti_sci_scan_clocks_from_dt(provider);
677*4882a593Smuzhiyun 	if (ret) {
678*4882a593Smuzhiyun 		dev_err(dev, "scan clocks from DT failed: %d\n", ret);
679*4882a593Smuzhiyun 		return ret;
680*4882a593Smuzhiyun 	}
681*4882a593Smuzhiyun #endif
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	ret = ti_sci_init_clocks(provider);
684*4882a593Smuzhiyun 	if (ret) {
685*4882a593Smuzhiyun 		pr_err("ti-sci-init-clocks failed.\n");
686*4882a593Smuzhiyun 		return ret;
687*4882a593Smuzhiyun 	}
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	return of_clk_add_hw_provider(np, sci_clk_get, provider);
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun /**
693*4882a593Smuzhiyun  * ti_sci_clk_remove - Remove TI SCI clock device
694*4882a593Smuzhiyun  * @pdev: platform device pointer for the device to be removed
695*4882a593Smuzhiyun  *
696*4882a593Smuzhiyun  * Removes the TI SCI device. Unregisters the clock provider registered
697*4882a593Smuzhiyun  * via common clock framework. Any memory allocated for the device will
698*4882a593Smuzhiyun  * be free'd silently via the devm framework. Returns 0 always.
699*4882a593Smuzhiyun  */
ti_sci_clk_remove(struct platform_device * pdev)700*4882a593Smuzhiyun static int ti_sci_clk_remove(struct platform_device *pdev)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun 	of_clk_del_provider(pdev->dev.of_node);
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun 	return 0;
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun static struct platform_driver ti_sci_clk_driver = {
708*4882a593Smuzhiyun 	.probe = ti_sci_clk_probe,
709*4882a593Smuzhiyun 	.remove = ti_sci_clk_remove,
710*4882a593Smuzhiyun 	.driver = {
711*4882a593Smuzhiyun 		.name = "ti-sci-clk",
712*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(ti_sci_clk_of_match),
713*4882a593Smuzhiyun 	},
714*4882a593Smuzhiyun };
715*4882a593Smuzhiyun module_platform_driver(ti_sci_clk_driver);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
718*4882a593Smuzhiyun MODULE_DESCRIPTION("TI System Control Interface(SCI) Clock driver");
719*4882a593Smuzhiyun MODULE_AUTHOR("Tero Kristo");
720*4882a593Smuzhiyun MODULE_ALIAS("platform:ti-sci-clk");
721