xref: /OK3568_Linux_fs/kernel/drivers/clk/ingenic/pm.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include "cgu.h"
7*4882a593Smuzhiyun #include "pm.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/syscore_ops.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define CGU_REG_LCR		0x04
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define LCR_LOW_POWER_MODE	BIT(0)
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun static void __iomem * __maybe_unused ingenic_cgu_base;
17*4882a593Smuzhiyun 
ingenic_cgu_pm_suspend(void)18*4882a593Smuzhiyun static int __maybe_unused ingenic_cgu_pm_suspend(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun 	return 0;
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun 
ingenic_cgu_pm_resume(void)27*4882a593Smuzhiyun static void __maybe_unused ingenic_cgu_pm_resume(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = {
35*4882a593Smuzhiyun 	.suspend = ingenic_cgu_pm_suspend,
36*4882a593Smuzhiyun 	.resume = ingenic_cgu_pm_resume,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
ingenic_cgu_register_syscore_ops(struct ingenic_cgu * cgu)39*4882a593Smuzhiyun void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
42*4882a593Smuzhiyun 		ingenic_cgu_base = cgu->base;
43*4882a593Smuzhiyun 		register_syscore_ops(&ingenic_cgu_pm_ops);
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun }
46