1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include "clk.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /**
13*4882a593Smuzhiyun * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
14*4882a593Smuzhiyun * exclusive with other gate clocks
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * @gate: the parent class
17*4882a593Smuzhiyun * @exclusive_mask: mask of gate bits which are mutually exclusive to this
18*4882a593Smuzhiyun * gate clock
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * The imx exclusive gate clock is a subclass of basic clk_gate
21*4882a593Smuzhiyun * with an addtional mask to indicate which other gate bits in the same
22*4882a593Smuzhiyun * register is mutually exclusive to this gate clock.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun struct clk_gate_exclusive {
25*4882a593Smuzhiyun struct clk_gate gate;
26*4882a593Smuzhiyun u32 exclusive_mask;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
clk_gate_exclusive_enable(struct clk_hw * hw)29*4882a593Smuzhiyun static int clk_gate_exclusive_enable(struct clk_hw *hw)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct clk_gate *gate = to_clk_gate(hw);
32*4882a593Smuzhiyun struct clk_gate_exclusive *exgate = container_of(gate,
33*4882a593Smuzhiyun struct clk_gate_exclusive, gate);
34*4882a593Smuzhiyun u32 val = readl(gate->reg);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (val & exgate->exclusive_mask)
37*4882a593Smuzhiyun return -EBUSY;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return clk_gate_ops.enable(hw);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
clk_gate_exclusive_disable(struct clk_hw * hw)42*4882a593Smuzhiyun static void clk_gate_exclusive_disable(struct clk_hw *hw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun clk_gate_ops.disable(hw);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
clk_gate_exclusive_is_enabled(struct clk_hw * hw)47*4882a593Smuzhiyun static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun return clk_gate_ops.is_enabled(hw);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct clk_ops clk_gate_exclusive_ops = {
53*4882a593Smuzhiyun .enable = clk_gate_exclusive_enable,
54*4882a593Smuzhiyun .disable = clk_gate_exclusive_disable,
55*4882a593Smuzhiyun .is_enabled = clk_gate_exclusive_is_enabled,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
imx_clk_hw_gate_exclusive(const char * name,const char * parent,void __iomem * reg,u8 shift,u32 exclusive_mask)58*4882a593Smuzhiyun struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
59*4882a593Smuzhiyun void __iomem *reg, u8 shift, u32 exclusive_mask)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct clk_gate_exclusive *exgate;
62*4882a593Smuzhiyun struct clk_gate *gate;
63*4882a593Smuzhiyun struct clk_hw *hw;
64*4882a593Smuzhiyun struct clk_init_data init;
65*4882a593Smuzhiyun int ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (exclusive_mask == 0)
68*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
71*4882a593Smuzhiyun if (!exgate)
72*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
73*4882a593Smuzhiyun gate = &exgate->gate;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun init.name = name;
76*4882a593Smuzhiyun init.ops = &clk_gate_exclusive_ops;
77*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
78*4882a593Smuzhiyun init.parent_names = parent ? &parent : NULL;
79*4882a593Smuzhiyun init.num_parents = parent ? 1 : 0;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun gate->reg = reg;
82*4882a593Smuzhiyun gate->bit_idx = shift;
83*4882a593Smuzhiyun gate->lock = &imx_ccm_lock;
84*4882a593Smuzhiyun gate->hw.init = &init;
85*4882a593Smuzhiyun exgate->exclusive_mask = exclusive_mask;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun hw = &gate->hw;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun ret = clk_hw_register(NULL, hw);
90*4882a593Smuzhiyun if (ret) {
91*4882a593Smuzhiyun kfree(gate);
92*4882a593Smuzhiyun return ERR_PTR(ret);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return hw;
96*4882a593Smuzhiyun }
97