1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bits.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include "clk.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /**
14*4882a593Smuzhiyun * struct clk_fixup_mux - imx integer fixup multiplexer clock
15*4882a593Smuzhiyun * @mux: the parent class
16*4882a593Smuzhiyun * @ops: pointer to clk_ops of parent class
17*4882a593Smuzhiyun * @fixup: a hook to fixup the write value
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * The imx fixup multiplexer clock is a subclass of basic clk_mux
20*4882a593Smuzhiyun * with an addtional fixup hook.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun struct clk_fixup_mux {
23*4882a593Smuzhiyun struct clk_mux mux;
24*4882a593Smuzhiyun const struct clk_ops *ops;
25*4882a593Smuzhiyun void (*fixup)(u32 *val);
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
to_clk_fixup_mux(struct clk_hw * hw)28*4882a593Smuzhiyun static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct clk_mux *mux = to_clk_mux(hw);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return container_of(mux, struct clk_fixup_mux, mux);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
clk_fixup_mux_get_parent(struct clk_hw * hw)35*4882a593Smuzhiyun static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
clk_fixup_mux_set_parent(struct clk_hw * hw,u8 index)42*4882a593Smuzhiyun static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
45*4882a593Smuzhiyun struct clk_mux *mux = to_clk_mux(hw);
46*4882a593Smuzhiyun unsigned long flags;
47*4882a593Smuzhiyun u32 val;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun spin_lock_irqsave(mux->lock, flags);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun val = readl(mux->reg);
52*4882a593Smuzhiyun val &= ~(mux->mask << mux->shift);
53*4882a593Smuzhiyun val |= index << mux->shift;
54*4882a593Smuzhiyun fixup_mux->fixup(&val);
55*4882a593Smuzhiyun writel(val, mux->reg);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun spin_unlock_irqrestore(mux->lock, flags);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct clk_ops clk_fixup_mux_ops = {
63*4882a593Smuzhiyun .get_parent = clk_fixup_mux_get_parent,
64*4882a593Smuzhiyun .set_parent = clk_fixup_mux_set_parent,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
imx_clk_hw_fixup_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,void (* fixup)(u32 * val))67*4882a593Smuzhiyun struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
68*4882a593Smuzhiyun u8 shift, u8 width, const char * const *parents,
69*4882a593Smuzhiyun int num_parents, void (*fixup)(u32 *val))
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct clk_fixup_mux *fixup_mux;
72*4882a593Smuzhiyun struct clk_hw *hw;
73*4882a593Smuzhiyun struct clk_init_data init;
74*4882a593Smuzhiyun int ret;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (!fixup)
77*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
80*4882a593Smuzhiyun if (!fixup_mux)
81*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun init.name = name;
84*4882a593Smuzhiyun init.ops = &clk_fixup_mux_ops;
85*4882a593Smuzhiyun init.parent_names = parents;
86*4882a593Smuzhiyun init.num_parents = num_parents;
87*4882a593Smuzhiyun init.flags = 0;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun fixup_mux->mux.reg = reg;
90*4882a593Smuzhiyun fixup_mux->mux.shift = shift;
91*4882a593Smuzhiyun fixup_mux->mux.mask = BIT(width) - 1;
92*4882a593Smuzhiyun fixup_mux->mux.lock = &imx_ccm_lock;
93*4882a593Smuzhiyun fixup_mux->mux.hw.init = &init;
94*4882a593Smuzhiyun fixup_mux->ops = &clk_mux_ops;
95*4882a593Smuzhiyun fixup_mux->fixup = fixup;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun hw = &fixup_mux->mux.hw;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = clk_hw_register(NULL, hw);
100*4882a593Smuzhiyun if (ret) {
101*4882a593Smuzhiyun kfree(fixup_mux);
102*4882a593Smuzhiyun return ERR_PTR(ret);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return hw;
106*4882a593Smuzhiyun }
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