1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/export.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include "clk.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct clk_cpu {
13*4882a593Smuzhiyun struct clk_hw hw;
14*4882a593Smuzhiyun struct clk *div;
15*4882a593Smuzhiyun struct clk *mux;
16*4882a593Smuzhiyun struct clk *pll;
17*4882a593Smuzhiyun struct clk *step;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
to_clk_cpu(struct clk_hw * hw)20*4882a593Smuzhiyun static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return container_of(hw, struct clk_cpu, hw);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
clk_cpu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)25*4882a593Smuzhiyun static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
26*4882a593Smuzhiyun unsigned long parent_rate)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun struct clk_cpu *cpu = to_clk_cpu(hw);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return clk_get_rate(cpu->div);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
clk_cpu_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)33*4882a593Smuzhiyun static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
34*4882a593Smuzhiyun unsigned long *prate)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct clk_cpu *cpu = to_clk_cpu(hw);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return clk_round_rate(cpu->pll, rate);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
clk_cpu_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)41*4882a593Smuzhiyun static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
42*4882a593Smuzhiyun unsigned long parent_rate)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct clk_cpu *cpu = to_clk_cpu(hw);
45*4882a593Smuzhiyun int ret;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* switch to PLL bypass clock */
48*4882a593Smuzhiyun ret = clk_set_parent(cpu->mux, cpu->step);
49*4882a593Smuzhiyun if (ret)
50*4882a593Smuzhiyun return ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* reprogram PLL */
53*4882a593Smuzhiyun ret = clk_set_rate(cpu->pll, rate);
54*4882a593Smuzhiyun if (ret) {
55*4882a593Smuzhiyun clk_set_parent(cpu->mux, cpu->pll);
56*4882a593Smuzhiyun return ret;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun /* switch back to PLL clock */
59*4882a593Smuzhiyun clk_set_parent(cpu->mux, cpu->pll);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Ensure the divider is what we expect */
62*4882a593Smuzhiyun clk_set_rate(cpu->div, rate);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct clk_ops clk_cpu_ops = {
68*4882a593Smuzhiyun .recalc_rate = clk_cpu_recalc_rate,
69*4882a593Smuzhiyun .round_rate = clk_cpu_round_rate,
70*4882a593Smuzhiyun .set_rate = clk_cpu_set_rate,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
imx_clk_hw_cpu(const char * name,const char * parent_name,struct clk * div,struct clk * mux,struct clk * pll,struct clk * step)73*4882a593Smuzhiyun struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
74*4882a593Smuzhiyun struct clk *div, struct clk *mux, struct clk *pll,
75*4882a593Smuzhiyun struct clk *step)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct clk_cpu *cpu;
78*4882a593Smuzhiyun struct clk_hw *hw;
79*4882a593Smuzhiyun struct clk_init_data init;
80*4882a593Smuzhiyun int ret;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
83*4882a593Smuzhiyun if (!cpu)
84*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun cpu->div = div;
87*4882a593Smuzhiyun cpu->mux = mux;
88*4882a593Smuzhiyun cpu->pll = pll;
89*4882a593Smuzhiyun cpu->step = step;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun init.name = name;
92*4882a593Smuzhiyun init.ops = &clk_cpu_ops;
93*4882a593Smuzhiyun init.flags = CLK_IS_CRITICAL;
94*4882a593Smuzhiyun init.parent_names = &parent_name;
95*4882a593Smuzhiyun init.num_parents = 1;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun cpu->hw.init = &init;
98*4882a593Smuzhiyun hw = &cpu->hw;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = clk_hw_register(NULL, hw);
101*4882a593Smuzhiyun if (ret) {
102*4882a593Smuzhiyun kfree(cpu);
103*4882a593Smuzhiyun return ERR_PTR(ret);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return hw;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(imx_clk_hw_cpu);
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