1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * Copyright 2017~2018 NXP
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bits.h>
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "clk.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define PCG_PCS_SHIFT 24
16*4882a593Smuzhiyun #define PCG_PCS_MASK 0x7
17*4882a593Smuzhiyun #define PCG_CGC_SHIFT 30
18*4882a593Smuzhiyun #define PCG_FRAC_SHIFT 3
19*4882a593Smuzhiyun #define PCG_FRAC_WIDTH 1
20*4882a593Smuzhiyun #define PCG_FRAC_MASK BIT(3)
21*4882a593Smuzhiyun #define PCG_PCD_SHIFT 0
22*4882a593Smuzhiyun #define PCG_PCD_WIDTH 3
23*4882a593Smuzhiyun #define PCG_PCD_MASK 0x7
24*4882a593Smuzhiyun
imx7ulp_clk_hw_composite(const char * name,const char * const * parent_names,int num_parents,bool mux_present,bool rate_present,bool gate_present,void __iomem * reg)25*4882a593Smuzhiyun struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
26*4882a593Smuzhiyun const char * const *parent_names,
27*4882a593Smuzhiyun int num_parents, bool mux_present,
28*4882a593Smuzhiyun bool rate_present, bool gate_present,
29*4882a593Smuzhiyun void __iomem *reg)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
32*4882a593Smuzhiyun struct clk_fractional_divider *fd = NULL;
33*4882a593Smuzhiyun struct clk_gate *gate = NULL;
34*4882a593Smuzhiyun struct clk_mux *mux = NULL;
35*4882a593Smuzhiyun struct clk_hw *hw;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (mux_present) {
38*4882a593Smuzhiyun mux = kzalloc(sizeof(*mux), GFP_KERNEL);
39*4882a593Smuzhiyun if (!mux)
40*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
41*4882a593Smuzhiyun mux_hw = &mux->hw;
42*4882a593Smuzhiyun mux->reg = reg;
43*4882a593Smuzhiyun mux->shift = PCG_PCS_SHIFT;
44*4882a593Smuzhiyun mux->mask = PCG_PCS_MASK;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (rate_present) {
48*4882a593Smuzhiyun fd = kzalloc(sizeof(*fd), GFP_KERNEL);
49*4882a593Smuzhiyun if (!fd) {
50*4882a593Smuzhiyun kfree(mux);
51*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun fd_hw = &fd->hw;
54*4882a593Smuzhiyun fd->reg = reg;
55*4882a593Smuzhiyun fd->mshift = PCG_FRAC_SHIFT;
56*4882a593Smuzhiyun fd->mwidth = PCG_FRAC_WIDTH;
57*4882a593Smuzhiyun fd->mmask = PCG_FRAC_MASK;
58*4882a593Smuzhiyun fd->nshift = PCG_PCD_SHIFT;
59*4882a593Smuzhiyun fd->nwidth = PCG_PCD_WIDTH;
60*4882a593Smuzhiyun fd->nmask = PCG_PCD_MASK;
61*4882a593Smuzhiyun fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (gate_present) {
65*4882a593Smuzhiyun gate = kzalloc(sizeof(*gate), GFP_KERNEL);
66*4882a593Smuzhiyun if (!gate) {
67*4882a593Smuzhiyun kfree(mux);
68*4882a593Smuzhiyun kfree(fd);
69*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun gate_hw = &gate->hw;
72*4882a593Smuzhiyun gate->reg = reg;
73*4882a593Smuzhiyun gate->bit_idx = PCG_CGC_SHIFT;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
77*4882a593Smuzhiyun mux_hw, &clk_mux_ops, fd_hw,
78*4882a593Smuzhiyun &clk_fractional_divider_ops, gate_hw,
79*4882a593Smuzhiyun &clk_gate_ops, CLK_SET_RATE_GATE |
80*4882a593Smuzhiyun CLK_SET_PARENT_GATE);
81*4882a593Smuzhiyun if (IS_ERR(hw)) {
82*4882a593Smuzhiyun kfree(mux);
83*4882a593Smuzhiyun kfree(fd);
84*4882a593Smuzhiyun kfree(gate);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return hw;
88*4882a593Smuzhiyun }
89