1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016-2017 Imagination Technologies
4*4882a593Smuzhiyun * Author: Paul Burton <paul.burton@mips.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define pr_fmt(fmt) "clk-boston: " fmt
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <dt-bindings/clock/boston-clock.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define BOSTON_PLAT_MMCMDIV 0x30
19*4882a593Smuzhiyun # define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
20*4882a593Smuzhiyun # define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
21*4882a593Smuzhiyun # define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
22*4882a593Smuzhiyun # define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define BOSTON_CLK_COUNT 3
25*4882a593Smuzhiyun
ext_field(u32 val,u32 mask)26*4882a593Smuzhiyun static u32 ext_field(u32 val, u32 mask)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun return (val & mask) >> (ffs(mask) - 1);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
clk_boston_setup(struct device_node * np)31*4882a593Smuzhiyun static void __init clk_boston_setup(struct device_node *np)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun unsigned long in_freq, cpu_freq, sys_freq;
34*4882a593Smuzhiyun uint mmcmdiv, mul, cpu_div, sys_div;
35*4882a593Smuzhiyun struct clk_hw_onecell_data *onecell;
36*4882a593Smuzhiyun struct regmap *regmap;
37*4882a593Smuzhiyun struct clk_hw *hw;
38*4882a593Smuzhiyun int err;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun regmap = syscon_node_to_regmap(np->parent);
41*4882a593Smuzhiyun if (IS_ERR(regmap)) {
42*4882a593Smuzhiyun pr_err("failed to find regmap\n");
43*4882a593Smuzhiyun return;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
47*4882a593Smuzhiyun if (err) {
48*4882a593Smuzhiyun pr_err("failed to read mmcm_div register: %d\n", err);
49*4882a593Smuzhiyun return;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
53*4882a593Smuzhiyun mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
56*4882a593Smuzhiyun sys_freq = mult_frac(in_freq, mul, sys_div);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
59*4882a593Smuzhiyun cpu_freq = mult_frac(in_freq, mul, cpu_div);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT),
62*4882a593Smuzhiyun GFP_KERNEL);
63*4882a593Smuzhiyun if (!onecell)
64*4882a593Smuzhiyun return;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun onecell->num = BOSTON_CLK_COUNT;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
69*4882a593Smuzhiyun if (IS_ERR(hw)) {
70*4882a593Smuzhiyun pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
71*4882a593Smuzhiyun goto fail_input;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun onecell->hws[BOSTON_CLK_INPUT] = hw;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
76*4882a593Smuzhiyun if (IS_ERR(hw)) {
77*4882a593Smuzhiyun pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
78*4882a593Smuzhiyun goto fail_sys;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun onecell->hws[BOSTON_CLK_SYS] = hw;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
83*4882a593Smuzhiyun if (IS_ERR(hw)) {
84*4882a593Smuzhiyun pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
85*4882a593Smuzhiyun goto fail_cpu;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun onecell->hws[BOSTON_CLK_CPU] = hw;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
90*4882a593Smuzhiyun if (err) {
91*4882a593Smuzhiyun pr_err("failed to add DT provider: %d\n", err);
92*4882a593Smuzhiyun goto fail_clk_add;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun fail_clk_add:
98*4882a593Smuzhiyun clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]);
99*4882a593Smuzhiyun fail_cpu:
100*4882a593Smuzhiyun clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]);
101*4882a593Smuzhiyun fail_sys:
102*4882a593Smuzhiyun clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]);
103*4882a593Smuzhiyun fail_input:
104*4882a593Smuzhiyun kfree(onecell);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
109*4882a593Smuzhiyun * CPU frequency for use with the GIC or cop0 counters/timers.
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
112