1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hisilicon HiP04 clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013-2014 Hisilicon Limited.
6*4882a593Smuzhiyun * Copyright (c) 2013-2014 Linaro Limited.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/clk-provider.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <dt-bindings/clock/hip04-clock.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "clk.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* fixed rate clocks */
24*4882a593Smuzhiyun static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
25*4882a593Smuzhiyun { HIP04_OSC50M, "osc50m", NULL, 0, 50000000, },
26*4882a593Smuzhiyun { HIP04_CLK_50M, "clk50m", NULL, 0, 50000000, },
27*4882a593Smuzhiyun { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, },
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
hip04_clk_init(struct device_node * np)30*4882a593Smuzhiyun static void __init hip04_clk_init(struct device_node *np)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct hisi_clock_data *clk_data;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
35*4882a593Smuzhiyun if (!clk_data)
36*4882a593Smuzhiyun return;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
39*4882a593Smuzhiyun ARRAY_SIZE(hip04_fixed_rate_clks),
40*4882a593Smuzhiyun clk_data);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
43