1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hisilicon clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013-2017 Hisilicon Limited.
6*4882a593Smuzhiyun * Copyright (c) 2017 Linaro Limited.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Kai Zhao <zhaokai1@hisilicon.com>
9*4882a593Smuzhiyun * Tao Wang <kevin.wangtao@hisilicon.com>
10*4882a593Smuzhiyun * Leo Yan <leo.yan@linaro.org>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk-provider.h>
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/err.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/mailbox_client.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <dt-bindings/clock/hi3660-clock.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define HI3660_STUB_CLOCK_DATA (0x70)
25*4882a593Smuzhiyun #define MHZ (1000 * 1000)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define DEFINE_CLK_STUB(_id, _cmd, _name) \
28*4882a593Smuzhiyun { \
29*4882a593Smuzhiyun .id = (_id), \
30*4882a593Smuzhiyun .cmd = (_cmd), \
31*4882a593Smuzhiyun .hw.init = &(struct clk_init_data) { \
32*4882a593Smuzhiyun .name = #_name, \
33*4882a593Smuzhiyun .ops = &hi3660_stub_clk_ops, \
34*4882a593Smuzhiyun .num_parents = 0, \
35*4882a593Smuzhiyun .flags = CLK_GET_RATE_NOCACHE, \
36*4882a593Smuzhiyun }, \
37*4882a593Smuzhiyun },
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct hi3660_stub_clk_chan {
42*4882a593Smuzhiyun struct mbox_client cl;
43*4882a593Smuzhiyun struct mbox_chan *mbox;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct hi3660_stub_clk {
47*4882a593Smuzhiyun unsigned int id;
48*4882a593Smuzhiyun struct clk_hw hw;
49*4882a593Smuzhiyun unsigned int cmd;
50*4882a593Smuzhiyun unsigned int msg[8];
51*4882a593Smuzhiyun unsigned int rate;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static void __iomem *freq_reg;
55*4882a593Smuzhiyun static struct hi3660_stub_clk_chan stub_clk_chan;
56*4882a593Smuzhiyun
hi3660_stub_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)57*4882a593Smuzhiyun static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw,
58*4882a593Smuzhiyun unsigned long parent_rate)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * LPM3 writes back the CPU frequency in shared SRAM so read
64*4882a593Smuzhiyun * back the frequency.
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ;
67*4882a593Smuzhiyun return stub_clk->rate;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
hi3660_stub_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)70*4882a593Smuzhiyun static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
71*4882a593Smuzhiyun unsigned long *prate)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * LPM3 handles rate rounding so just return whatever
75*4882a593Smuzhiyun * rate is requested.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun return rate;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
hi3660_stub_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)80*4882a593Smuzhiyun static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
81*4882a593Smuzhiyun unsigned long parent_rate)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun stub_clk->msg[0] = stub_clk->cmd;
86*4882a593Smuzhiyun stub_clk->msg[1] = rate / MHZ;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n",
89*4882a593Smuzhiyun stub_clk->msg[0], stub_clk->msg[1]);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun mbox_send_message(stub_clk_chan.mbox, stub_clk->msg);
92*4882a593Smuzhiyun mbox_client_txdone(stub_clk_chan.mbox, 0);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun stub_clk->rate = rate;
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct clk_ops hi3660_stub_clk_ops = {
99*4882a593Smuzhiyun .recalc_rate = hi3660_stub_clk_recalc_rate,
100*4882a593Smuzhiyun .round_rate = hi3660_stub_clk_round_rate,
101*4882a593Smuzhiyun .set_rate = hi3660_stub_clk_set_rate,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = {
105*4882a593Smuzhiyun DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0")
106*4882a593Smuzhiyun DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1")
107*4882a593Smuzhiyun DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
108*4882a593Smuzhiyun DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
hi3660_stub_clk_hw_get(struct of_phandle_args * clkspec,void * data)111*4882a593Smuzhiyun static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
112*4882a593Smuzhiyun void *data)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun unsigned int idx = clkspec->args[0];
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (idx >= HI3660_CLK_STUB_NUM) {
117*4882a593Smuzhiyun pr_err("%s: invalid index %u\n", __func__, idx);
118*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return &hi3660_stub_clks[idx].hw;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
hi3660_stub_clk_probe(struct platform_device * pdev)124*4882a593Smuzhiyun static int hi3660_stub_clk_probe(struct platform_device *pdev)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct device *dev = &pdev->dev;
127*4882a593Smuzhiyun struct resource *res;
128*4882a593Smuzhiyun unsigned int i;
129*4882a593Smuzhiyun int ret;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Use mailbox client without blocking */
132*4882a593Smuzhiyun stub_clk_chan.cl.dev = dev;
133*4882a593Smuzhiyun stub_clk_chan.cl.tx_done = NULL;
134*4882a593Smuzhiyun stub_clk_chan.cl.tx_block = false;
135*4882a593Smuzhiyun stub_clk_chan.cl.knows_txdone = false;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Allocate mailbox channel */
138*4882a593Smuzhiyun stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
139*4882a593Smuzhiyun if (IS_ERR(stub_clk_chan.mbox))
140*4882a593Smuzhiyun return PTR_ERR(stub_clk_chan.mbox);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
143*4882a593Smuzhiyun if (!res)
144*4882a593Smuzhiyun return -EINVAL;
145*4882a593Smuzhiyun freq_reg = devm_ioremap(dev, res->start, resource_size(res));
146*4882a593Smuzhiyun if (!freq_reg)
147*4882a593Smuzhiyun return -ENOMEM;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun freq_reg += HI3660_STUB_CLOCK_DATA;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
152*4882a593Smuzhiyun ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
153*4882a593Smuzhiyun if (ret)
154*4882a593Smuzhiyun return ret;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(&pdev->dev, hi3660_stub_clk_hw_get,
158*4882a593Smuzhiyun hi3660_stub_clks);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static const struct of_device_id hi3660_stub_clk_of_match[] = {
162*4882a593Smuzhiyun { .compatible = "hisilicon,hi3660-stub-clk", },
163*4882a593Smuzhiyun {}
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static struct platform_driver hi3660_stub_clk_driver = {
167*4882a593Smuzhiyun .probe = hi3660_stub_clk_probe,
168*4882a593Smuzhiyun .driver = {
169*4882a593Smuzhiyun .name = "hi3660-stub-clk",
170*4882a593Smuzhiyun .of_match_table = hi3660_stub_clk_of_match,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
hi3660_stub_clk_init(void)174*4882a593Smuzhiyun static int __init hi3660_stub_clk_init(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun return platform_driver_register(&hi3660_stub_clk_driver);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun subsys_initcall(hi3660_stub_clk_init);
179