1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * H8S2678 clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static DEFINE_SPINLOCK(clklock);
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MAX_FREQ 33333333
18*4882a593Smuzhiyun #define MIN_FREQ 8000000
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct pll_clock {
21*4882a593Smuzhiyun struct clk_hw hw;
22*4882a593Smuzhiyun void __iomem *sckcr;
23*4882a593Smuzhiyun void __iomem *pllcr;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
27*4882a593Smuzhiyun
pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)28*4882a593Smuzhiyun static unsigned long pll_recalc_rate(struct clk_hw *hw,
29*4882a593Smuzhiyun unsigned long parent_rate)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct pll_clock *pll_clock = to_pll_clock(hw);
32*4882a593Smuzhiyun int mul = 1 << (readb(pll_clock->pllcr) & 3);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return parent_rate * mul;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)37*4882a593Smuzhiyun static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
38*4882a593Smuzhiyun unsigned long *prate)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun int i, m = -1;
41*4882a593Smuzhiyun long offset[3];
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (rate > MAX_FREQ)
44*4882a593Smuzhiyun rate = MAX_FREQ;
45*4882a593Smuzhiyun if (rate < MIN_FREQ)
46*4882a593Smuzhiyun rate = MIN_FREQ;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun for (i = 0; i < 3; i++)
49*4882a593Smuzhiyun offset[i] = abs(rate - (*prate * (1 << i)));
50*4882a593Smuzhiyun for (i = 0; i < 3; i++)
51*4882a593Smuzhiyun if (m < 0)
52*4882a593Smuzhiyun m = i;
53*4882a593Smuzhiyun else
54*4882a593Smuzhiyun m = (offset[i] < offset[m])?i:m;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return *prate * (1 << m);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)59*4882a593Smuzhiyun static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
60*4882a593Smuzhiyun unsigned long parent_rate)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun int pll;
63*4882a593Smuzhiyun unsigned char val;
64*4882a593Smuzhiyun unsigned long flags;
65*4882a593Smuzhiyun struct pll_clock *pll_clock = to_pll_clock(hw);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun pll = ((rate / parent_rate) / 2) & 0x03;
68*4882a593Smuzhiyun spin_lock_irqsave(&clklock, flags);
69*4882a593Smuzhiyun val = readb(pll_clock->sckcr);
70*4882a593Smuzhiyun val |= 0x08;
71*4882a593Smuzhiyun writeb(val, pll_clock->sckcr);
72*4882a593Smuzhiyun val = readb(pll_clock->pllcr);
73*4882a593Smuzhiyun val &= ~0x03;
74*4882a593Smuzhiyun val |= pll;
75*4882a593Smuzhiyun writeb(val, pll_clock->pllcr);
76*4882a593Smuzhiyun spin_unlock_irqrestore(&clklock, flags);
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct clk_ops pll_ops = {
81*4882a593Smuzhiyun .recalc_rate = pll_recalc_rate,
82*4882a593Smuzhiyun .round_rate = pll_round_rate,
83*4882a593Smuzhiyun .set_rate = pll_set_rate,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
h8s2678_pll_clk_setup(struct device_node * node)86*4882a593Smuzhiyun static void __init h8s2678_pll_clk_setup(struct device_node *node)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun unsigned int num_parents;
89*4882a593Smuzhiyun const char *clk_name = node->name;
90*4882a593Smuzhiyun const char *parent_name;
91*4882a593Smuzhiyun struct pll_clock *pll_clock;
92*4882a593Smuzhiyun struct clk_init_data init;
93*4882a593Smuzhiyun int ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun num_parents = of_clk_get_parent_count(node);
96*4882a593Smuzhiyun if (!num_parents) {
97*4882a593Smuzhiyun pr_err("%s: no parent found\n", clk_name);
98*4882a593Smuzhiyun return;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
103*4882a593Smuzhiyun if (!pll_clock)
104*4882a593Smuzhiyun return;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun pll_clock->sckcr = of_iomap(node, 0);
107*4882a593Smuzhiyun if (pll_clock->sckcr == NULL) {
108*4882a593Smuzhiyun pr_err("%s: failed to map divide register\n", clk_name);
109*4882a593Smuzhiyun goto free_clock;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun pll_clock->pllcr = of_iomap(node, 1);
113*4882a593Smuzhiyun if (pll_clock->pllcr == NULL) {
114*4882a593Smuzhiyun pr_err("%s: failed to map multiply register\n", clk_name);
115*4882a593Smuzhiyun goto unmap_sckcr;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(node, 0);
119*4882a593Smuzhiyun init.name = clk_name;
120*4882a593Smuzhiyun init.ops = &pll_ops;
121*4882a593Smuzhiyun init.flags = 0;
122*4882a593Smuzhiyun init.parent_names = &parent_name;
123*4882a593Smuzhiyun init.num_parents = 1;
124*4882a593Smuzhiyun pll_clock->hw.init = &init;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun ret = clk_hw_register(NULL, &pll_clock->hw);
127*4882a593Smuzhiyun if (ret) {
128*4882a593Smuzhiyun pr_err("%s: failed to register %s div clock (%d)\n",
129*4882a593Smuzhiyun __func__, clk_name, ret);
130*4882a593Smuzhiyun goto unmap_pllcr;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
134*4882a593Smuzhiyun return;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun unmap_pllcr:
137*4882a593Smuzhiyun iounmap(pll_clock->pllcr);
138*4882a593Smuzhiyun unmap_sckcr:
139*4882a593Smuzhiyun iounmap(pll_clock->sckcr);
140*4882a593Smuzhiyun free_clock:
141*4882a593Smuzhiyun kfree(pll_clock);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
145*4882a593Smuzhiyun h8s2678_pll_clk_setup);
146