1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * H8/300 divide clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static DEFINE_SPINLOCK(clklock);
15*4882a593Smuzhiyun
h8300_div_clk_setup(struct device_node * node)16*4882a593Smuzhiyun static void __init h8300_div_clk_setup(struct device_node *node)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun unsigned int num_parents;
19*4882a593Smuzhiyun struct clk_hw *hw;
20*4882a593Smuzhiyun const char *clk_name = node->name;
21*4882a593Smuzhiyun const char *parent_name;
22*4882a593Smuzhiyun void __iomem *divcr = NULL;
23*4882a593Smuzhiyun int width;
24*4882a593Smuzhiyun int offset;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun num_parents = of_clk_get_parent_count(node);
27*4882a593Smuzhiyun if (!num_parents) {
28*4882a593Smuzhiyun pr_err("%s: no parent found\n", clk_name);
29*4882a593Smuzhiyun return;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun divcr = of_iomap(node, 0);
33*4882a593Smuzhiyun if (divcr == NULL) {
34*4882a593Smuzhiyun pr_err("%s: failed to map divide register\n", clk_name);
35*4882a593Smuzhiyun goto error;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun offset = (unsigned long)divcr & 3;
38*4882a593Smuzhiyun offset = (3 - offset) * 8;
39*4882a593Smuzhiyun divcr = (void __iomem *)((unsigned long)divcr & ~3);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(node, 0);
42*4882a593Smuzhiyun of_property_read_u32(node, "renesas,width", &width);
43*4882a593Smuzhiyun hw = clk_hw_register_divider(NULL, clk_name, parent_name,
44*4882a593Smuzhiyun CLK_SET_RATE_GATE, divcr, offset, width,
45*4882a593Smuzhiyun CLK_DIVIDER_POWER_OF_TWO, &clklock);
46*4882a593Smuzhiyun if (!IS_ERR(hw)) {
47*4882a593Smuzhiyun of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
48*4882a593Smuzhiyun return;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun pr_err("%s: failed to register %s div clock (%ld)\n",
51*4882a593Smuzhiyun __func__, clk_name, PTR_ERR(hw));
52*4882a593Smuzhiyun error:
53*4882a593Smuzhiyun if (divcr)
54*4882a593Smuzhiyun iounmap(divcr);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);
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