1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Clock driver for TI Davinci PSC controllers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 David Lechner <david@lechnology.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CLK_DAVINCI_PSC_H__ 9*4882a593Smuzhiyun #define __CLK_DAVINCI_PSC_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/clk-provider.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* PSC quirk flags */ 15*4882a593Smuzhiyun #define LPSC_ALWAYS_ENABLED BIT(0) /* never disable this clock */ 16*4882a593Smuzhiyun #define LPSC_SET_RATE_PARENT BIT(1) /* propagate set_rate to parent clock */ 17*4882a593Smuzhiyun #define LPSC_FORCE BIT(2) /* requires MDCTL FORCE bit */ 18*4882a593Smuzhiyun #define LPSC_LOCAL_RESET BIT(3) /* acts as reset provider */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct davinci_lpsc_clkdev_info { 21*4882a593Smuzhiyun const char *con_id; 22*4882a593Smuzhiyun const char *dev_id; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define LPSC_CLKDEV(c, d) { \ 26*4882a593Smuzhiyun .con_id = (c), \ 27*4882a593Smuzhiyun .dev_id = (d) \ 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define LPSC_CLKDEV1(n, c, d) \ 31*4882a593Smuzhiyun static const struct davinci_lpsc_clkdev_info n[] __initconst = { \ 32*4882a593Smuzhiyun LPSC_CLKDEV((c), (d)), \ 33*4882a593Smuzhiyun { } \ 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define LPSC_CLKDEV2(n, c1, d1, c2, d2) \ 37*4882a593Smuzhiyun static const struct davinci_lpsc_clkdev_info n[] __initconst = { \ 38*4882a593Smuzhiyun LPSC_CLKDEV((c1), (d1)), \ 39*4882a593Smuzhiyun LPSC_CLKDEV((c2), (d2)), \ 40*4882a593Smuzhiyun { } \ 41*4882a593Smuzhiyun } 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define LPSC_CLKDEV3(n, c1, d1, c2, d2, c3, d3) \ 44*4882a593Smuzhiyun static const struct davinci_lpsc_clkdev_info n[] __initconst = { \ 45*4882a593Smuzhiyun LPSC_CLKDEV((c1), (d1)), \ 46*4882a593Smuzhiyun LPSC_CLKDEV((c2), (d2)), \ 47*4882a593Smuzhiyun LPSC_CLKDEV((c3), (d3)), \ 48*4882a593Smuzhiyun { } \ 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /** 52*4882a593Smuzhiyun * davinci_lpsc_clk_info - LPSC module-specific clock information 53*4882a593Smuzhiyun * @name: the clock name 54*4882a593Smuzhiyun * @parent: the parent clock name 55*4882a593Smuzhiyun * @cdevs: optional array of clkdev lookup table info 56*4882a593Smuzhiyun * @md: the local module domain (LPSC id) 57*4882a593Smuzhiyun * @pd: the power domain id 58*4882a593Smuzhiyun * @flags: bitmask of LPSC_* flags 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun struct davinci_lpsc_clk_info { 61*4882a593Smuzhiyun const char *name; 62*4882a593Smuzhiyun const char *parent; 63*4882a593Smuzhiyun const struct davinci_lpsc_clkdev_info *cdevs; 64*4882a593Smuzhiyun u32 md; 65*4882a593Smuzhiyun u32 pd; 66*4882a593Smuzhiyun unsigned long flags; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define LPSC(m, d, n, p, c, f) \ 70*4882a593Smuzhiyun { \ 71*4882a593Smuzhiyun .name = #n, \ 72*4882a593Smuzhiyun .parent = #p, \ 73*4882a593Smuzhiyun .cdevs = (c), \ 74*4882a593Smuzhiyun .md = (m), \ 75*4882a593Smuzhiyun .pd = (d), \ 76*4882a593Smuzhiyun .flags = (f), \ 77*4882a593Smuzhiyun } 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun int davinci_psc_register_clocks(struct device *dev, 80*4882a593Smuzhiyun const struct davinci_lpsc_clk_info *info, 81*4882a593Smuzhiyun u8 num_clks, 82*4882a593Smuzhiyun void __iomem *base); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int of_davinci_psc_clk_init(struct device *dev, 85*4882a593Smuzhiyun const struct davinci_lpsc_clk_info *info, 86*4882a593Smuzhiyun u8 num_clks, 87*4882a593Smuzhiyun void __iomem *base); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Device-specific data */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct davinci_psc_init_data { 92*4882a593Smuzhiyun struct clk_bulk_data *parent_clks; 93*4882a593Smuzhiyun int num_parent_clks; 94*4882a593Smuzhiyun int (*psc_init)(struct device *dev, void __iomem *base); 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DA830 98*4882a593Smuzhiyun extern const struct davinci_psc_init_data da830_psc0_init_data; 99*4882a593Smuzhiyun extern const struct davinci_psc_init_data da830_psc1_init_data; 100*4882a593Smuzhiyun #endif 101*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DA850 102*4882a593Smuzhiyun extern const struct davinci_psc_init_data da850_psc0_init_data; 103*4882a593Smuzhiyun extern const struct davinci_psc_init_data da850_psc1_init_data; 104*4882a593Smuzhiyun extern const struct davinci_psc_init_data of_da850_psc0_init_data; 105*4882a593Smuzhiyun extern const struct davinci_psc_init_data of_da850_psc1_init_data; 106*4882a593Smuzhiyun #endif 107*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DM355 108*4882a593Smuzhiyun extern const struct davinci_psc_init_data dm355_psc_init_data; 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DM365 111*4882a593Smuzhiyun extern const struct davinci_psc_init_data dm365_psc_init_data; 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DM644x 114*4882a593Smuzhiyun extern const struct davinci_psc_init_data dm644x_psc_init_data; 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DAVINCI_DM646x 117*4882a593Smuzhiyun extern const struct davinci_psc_init_data dm646x_psc_init_data; 118*4882a593Smuzhiyun #endif 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __CLK_DAVINCI_PSC_H__ */ 121