1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 David Lechner <david@lechnology.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clkdev.h>
9*4882a593Smuzhiyun #include <linux/clk/davinci.h>
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "pll.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static const struct davinci_pll_clk_info da830_pll_info = {
17*4882a593Smuzhiyun .name = "pll0",
18*4882a593Smuzhiyun .pllm_mask = GENMASK(4, 0),
19*4882a593Smuzhiyun .pllm_min = 4,
20*4882a593Smuzhiyun .pllm_max = 32,
21*4882a593Smuzhiyun .pllout_min_rate = 300000000,
22*4882a593Smuzhiyun .pllout_max_rate = 600000000,
23*4882a593Smuzhiyun .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
28*4882a593Smuzhiyun * meaning that we could change the divider as long as we keep the correct
29*4882a593Smuzhiyun * ratio between all of the clocks, but we don't support that because there is
30*4882a593Smuzhiyun * currently not a need for it.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
34*4882a593Smuzhiyun SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
35*4882a593Smuzhiyun SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
36*4882a593Smuzhiyun SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
37*4882a593Smuzhiyun SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
38*4882a593Smuzhiyun SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
39*4882a593Smuzhiyun
da830_pll_init(struct device * dev,void __iomem * base,struct regmap * cfgchip)40*4882a593Smuzhiyun int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct clk *clk;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
47*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
48*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
51*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
54*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
55*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
58*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
61*4882a593Smuzhiyun clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
66*4882a593Smuzhiyun clk_register_clkdev(clk, NULL, "i2c_davinci.1");
67*4882a593Smuzhiyun clk_register_clkdev(clk, "timer0", NULL);
68*4882a593Smuzhiyun clk_register_clkdev(clk, NULL, "davinci-wdt");
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
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