1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Clkout driver for Rockchip RK808
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author:Chris Zhong <zyw@rock-chips.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/mfd/rk808.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct rk808_clkout {
18*4882a593Smuzhiyun struct rk808 *rk808;
19*4882a593Smuzhiyun struct clk_hw clkout1_hw;
20*4882a593Smuzhiyun struct clk_hw clkout2_hw;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
rk808_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)23*4882a593Smuzhiyun static unsigned long rk808_clkout_recalc_rate(struct clk_hw *hw,
24*4882a593Smuzhiyun unsigned long parent_rate)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun return 32768;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
rk808_clkout2_enable(struct clk_hw * hw,bool enable)29*4882a593Smuzhiyun static int rk808_clkout2_enable(struct clk_hw *hw, bool enable)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout = container_of(hw,
32*4882a593Smuzhiyun struct rk808_clkout,
33*4882a593Smuzhiyun clkout2_hw);
34*4882a593Smuzhiyun struct rk808 *rk808 = rk808_clkout->rk808;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return regmap_update_bits(rk808->regmap, RK808_CLK32OUT_REG,
37*4882a593Smuzhiyun CLK32KOUT2_EN, enable ? CLK32KOUT2_EN : 0);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
rk808_clkout2_prepare(struct clk_hw * hw)40*4882a593Smuzhiyun static int rk808_clkout2_prepare(struct clk_hw *hw)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun return rk808_clkout2_enable(hw, true);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
rk808_clkout2_unprepare(struct clk_hw * hw)45*4882a593Smuzhiyun static void rk808_clkout2_unprepare(struct clk_hw *hw)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun rk808_clkout2_enable(hw, false);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
rk808_clkout2_is_prepared(struct clk_hw * hw)50*4882a593Smuzhiyun static int rk808_clkout2_is_prepared(struct clk_hw *hw)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout = container_of(hw,
53*4882a593Smuzhiyun struct rk808_clkout,
54*4882a593Smuzhiyun clkout2_hw);
55*4882a593Smuzhiyun struct rk808 *rk808 = rk808_clkout->rk808;
56*4882a593Smuzhiyun uint32_t val;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (ret < 0)
61*4882a593Smuzhiyun return ret;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return (val & CLK32KOUT2_EN) ? 1 : 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static const struct clk_ops rk808_clkout1_ops = {
67*4882a593Smuzhiyun .recalc_rate = rk808_clkout_recalc_rate,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct clk_ops rk808_clkout2_ops = {
71*4882a593Smuzhiyun .prepare = rk808_clkout2_prepare,
72*4882a593Smuzhiyun .unprepare = rk808_clkout2_unprepare,
73*4882a593Smuzhiyun .is_prepared = rk808_clkout2_is_prepared,
74*4882a593Smuzhiyun .recalc_rate = rk808_clkout_recalc_rate,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static struct clk_hw *
of_clk_rk808_get(struct of_phandle_args * clkspec,void * data)78*4882a593Smuzhiyun of_clk_rk808_get(struct of_phandle_args *clkspec, void *data)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout = data;
81*4882a593Smuzhiyun unsigned int idx = clkspec->args[0];
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (idx >= 2) {
84*4882a593Smuzhiyun pr_err("%s: invalid index %u\n", __func__, idx);
85*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return idx ? &rk808_clkout->clkout2_hw : &rk808_clkout->clkout1_hw;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
rk817_clkout2_enable(struct clk_hw * hw,bool enable)91*4882a593Smuzhiyun static int rk817_clkout2_enable(struct clk_hw *hw, bool enable)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout = container_of(hw,
94*4882a593Smuzhiyun struct rk808_clkout,
95*4882a593Smuzhiyun clkout2_hw);
96*4882a593Smuzhiyun struct rk808 *rk808 = rk808_clkout->rk808;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1),
99*4882a593Smuzhiyun RK817_CLK32KOUT2_EN,
100*4882a593Smuzhiyun enable ? RK817_CLK32KOUT2_EN : 0);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
rk817_clkout2_prepare(struct clk_hw * hw)103*4882a593Smuzhiyun static int rk817_clkout2_prepare(struct clk_hw *hw)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun return rk817_clkout2_enable(hw, true);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
rk817_clkout2_unprepare(struct clk_hw * hw)108*4882a593Smuzhiyun static void rk817_clkout2_unprepare(struct clk_hw *hw)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun rk817_clkout2_enable(hw, false);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
rk817_clkout2_is_prepared(struct clk_hw * hw)113*4882a593Smuzhiyun static int rk817_clkout2_is_prepared(struct clk_hw *hw)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout = container_of(hw,
116*4882a593Smuzhiyun struct rk808_clkout,
117*4882a593Smuzhiyun clkout2_hw);
118*4882a593Smuzhiyun struct rk808 *rk808 = rk808_clkout->rk808;
119*4882a593Smuzhiyun unsigned int val;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (ret < 0)
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return (val & RK817_CLK32KOUT2_EN) ? 1 : 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const struct clk_ops rk817_clkout2_ops = {
130*4882a593Smuzhiyun .prepare = rk817_clkout2_prepare,
131*4882a593Smuzhiyun .unprepare = rk817_clkout2_unprepare,
132*4882a593Smuzhiyun .is_prepared = rk817_clkout2_is_prepared,
133*4882a593Smuzhiyun .recalc_rate = rk808_clkout_recalc_rate,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
rkpmic_get_ops(long variant)136*4882a593Smuzhiyun static const struct clk_ops *rkpmic_get_ops(long variant)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun switch (variant) {
139*4882a593Smuzhiyun case RK809_ID:
140*4882a593Smuzhiyun case RK817_ID:
141*4882a593Smuzhiyun return &rk817_clkout2_ops;
142*4882a593Smuzhiyun /*
143*4882a593Smuzhiyun * For the default case, it match the following PMIC type.
144*4882a593Smuzhiyun * RK805_ID
145*4882a593Smuzhiyun * RK808_ID
146*4882a593Smuzhiyun * RK818_ID
147*4882a593Smuzhiyun */
148*4882a593Smuzhiyun default:
149*4882a593Smuzhiyun return &rk808_clkout2_ops;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
rk808_clkout_probe(struct platform_device * pdev)153*4882a593Smuzhiyun static int rk808_clkout_probe(struct platform_device *pdev)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
156*4882a593Smuzhiyun struct i2c_client *client = rk808->i2c;
157*4882a593Smuzhiyun struct device_node *node = client->dev.of_node;
158*4882a593Smuzhiyun struct clk_init_data init = {};
159*4882a593Smuzhiyun struct rk808_clkout *rk808_clkout;
160*4882a593Smuzhiyun int ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun rk808_clkout = devm_kzalloc(&client->dev,
163*4882a593Smuzhiyun sizeof(*rk808_clkout), GFP_KERNEL);
164*4882a593Smuzhiyun if (!rk808_clkout)
165*4882a593Smuzhiyun return -ENOMEM;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun rk808_clkout->rk808 = rk808;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun init.parent_names = NULL;
170*4882a593Smuzhiyun init.num_parents = 0;
171*4882a593Smuzhiyun init.name = "rk808-clkout1";
172*4882a593Smuzhiyun init.ops = &rk808_clkout1_ops;
173*4882a593Smuzhiyun rk808_clkout->clkout1_hw.init = &init;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* optional override of the clockname */
176*4882a593Smuzhiyun of_property_read_string_index(node, "clock-output-names",
177*4882a593Smuzhiyun 0, &init.name);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout1_hw);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun init.name = "rk808-clkout2";
184*4882a593Smuzhiyun init.ops = rkpmic_get_ops(rk808->variant);
185*4882a593Smuzhiyun rk808_clkout->clkout2_hw.init = &init;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* optional override of the clockname */
188*4882a593Smuzhiyun of_property_read_string_index(node, "clock-output-names",
189*4882a593Smuzhiyun 1, &init.name);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout2_hw);
192*4882a593Smuzhiyun if (ret)
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rk808_get,
196*4882a593Smuzhiyun rk808_clkout);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static struct platform_driver rk808_clkout_driver = {
200*4882a593Smuzhiyun .probe = rk808_clkout_probe,
201*4882a593Smuzhiyun .driver = {
202*4882a593Smuzhiyun .name = "rk808-clkout",
203*4882a593Smuzhiyun },
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun module_platform_driver(rk808_clkout_driver);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun MODULE_DESCRIPTION("Clkout driver for the rk808 series PMICs");
209*4882a593Smuzhiyun MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
210*4882a593Smuzhiyun MODULE_LICENSE("GPL");
211*4882a593Smuzhiyun MODULE_ALIAS("platform:rk808-clkout");
212