1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Philipp Zabel, Pengutronix
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * PWM (mis)used as clock output
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pwm.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct clk_pwm {
15*4882a593Smuzhiyun struct clk_hw hw;
16*4882a593Smuzhiyun struct pwm_device *pwm;
17*4882a593Smuzhiyun u32 fixed_rate;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
to_clk_pwm(struct clk_hw * hw)20*4882a593Smuzhiyun static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return container_of(hw, struct clk_pwm, hw);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
clk_pwm_prepare(struct clk_hw * hw)25*4882a593Smuzhiyun static int clk_pwm_prepare(struct clk_hw *hw)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct clk_pwm *clk_pwm = to_clk_pwm(hw);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return pwm_enable(clk_pwm->pwm);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
clk_pwm_unprepare(struct clk_hw * hw)32*4882a593Smuzhiyun static void clk_pwm_unprepare(struct clk_hw *hw)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct clk_pwm *clk_pwm = to_clk_pwm(hw);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun pwm_disable(clk_pwm->pwm);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
clk_pwm_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)39*4882a593Smuzhiyun static unsigned long clk_pwm_recalc_rate(struct clk_hw *hw,
40*4882a593Smuzhiyun unsigned long parent_rate)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct clk_pwm *clk_pwm = to_clk_pwm(hw);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return clk_pwm->fixed_rate;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
clk_pwm_get_duty_cycle(struct clk_hw * hw,struct clk_duty * duty)47*4882a593Smuzhiyun static int clk_pwm_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct clk_pwm *clk_pwm = to_clk_pwm(hw);
50*4882a593Smuzhiyun struct pwm_state state;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun pwm_get_state(clk_pwm->pwm, &state);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun duty->num = state.duty_cycle;
55*4882a593Smuzhiyun duty->den = state.period;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct clk_ops clk_pwm_ops = {
61*4882a593Smuzhiyun .prepare = clk_pwm_prepare,
62*4882a593Smuzhiyun .unprepare = clk_pwm_unprepare,
63*4882a593Smuzhiyun .recalc_rate = clk_pwm_recalc_rate,
64*4882a593Smuzhiyun .get_duty_cycle = clk_pwm_get_duty_cycle,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
clk_pwm_probe(struct platform_device * pdev)67*4882a593Smuzhiyun static int clk_pwm_probe(struct platform_device *pdev)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
70*4882a593Smuzhiyun struct clk_init_data init;
71*4882a593Smuzhiyun struct clk_pwm *clk_pwm;
72*4882a593Smuzhiyun struct pwm_device *pwm;
73*4882a593Smuzhiyun struct pwm_args pargs;
74*4882a593Smuzhiyun const char *clk_name;
75*4882a593Smuzhiyun int ret;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL);
78*4882a593Smuzhiyun if (!clk_pwm)
79*4882a593Smuzhiyun return -ENOMEM;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun pwm = devm_pwm_get(&pdev->dev, NULL);
82*4882a593Smuzhiyun if (IS_ERR(pwm))
83*4882a593Smuzhiyun return PTR_ERR(pwm);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun pwm_get_args(pwm, &pargs);
86*4882a593Smuzhiyun if (!pargs.period) {
87*4882a593Smuzhiyun dev_err(&pdev->dev, "invalid PWM period\n");
88*4882a593Smuzhiyun return -EINVAL;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
92*4882a593Smuzhiyun clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (!clk_pwm->fixed_rate) {
95*4882a593Smuzhiyun dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
96*4882a593Smuzhiyun return -EINVAL;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
100*4882a593Smuzhiyun pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
101*4882a593Smuzhiyun dev_err(&pdev->dev,
102*4882a593Smuzhiyun "clock-frequency does not match PWM period\n");
103*4882a593Smuzhiyun return -EINVAL;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun * FIXME: pwm_apply_args() should be removed when switching to the
108*4882a593Smuzhiyun * atomic PWM API.
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun pwm_apply_args(pwm);
111*4882a593Smuzhiyun ret = pwm_config(pwm, (pargs.period + 1) >> 1, pargs.period);
112*4882a593Smuzhiyun if (ret < 0)
113*4882a593Smuzhiyun return ret;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun clk_name = node->name;
116*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &clk_name);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun init.name = clk_name;
119*4882a593Smuzhiyun init.ops = &clk_pwm_ops;
120*4882a593Smuzhiyun init.flags = 0;
121*4882a593Smuzhiyun init.num_parents = 0;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun clk_pwm->pwm = pwm;
124*4882a593Smuzhiyun clk_pwm->hw.init = &init;
125*4882a593Smuzhiyun ret = devm_clk_hw_register(&pdev->dev, &clk_pwm->hw);
126*4882a593Smuzhiyun if (ret)
127*4882a593Smuzhiyun return ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
clk_pwm_remove(struct platform_device * pdev)132*4882a593Smuzhiyun static int clk_pwm_remove(struct platform_device *pdev)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun of_clk_del_provider(pdev->dev.of_node);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const struct of_device_id clk_pwm_dt_ids[] = {
140*4882a593Smuzhiyun { .compatible = "pwm-clock" },
141*4882a593Smuzhiyun { }
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static struct platform_driver clk_pwm_driver = {
146*4882a593Smuzhiyun .probe = clk_pwm_probe,
147*4882a593Smuzhiyun .remove = clk_pwm_remove,
148*4882a593Smuzhiyun .driver = {
149*4882a593Smuzhiyun .name = "pwm-clock",
150*4882a593Smuzhiyun .of_match_table = of_match_ptr(clk_pwm_dt_ids),
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun module_platform_driver(clk_pwm_driver);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
157*4882a593Smuzhiyun MODULE_DESCRIPTION("PWM clock driver");
158*4882a593Smuzhiyun MODULE_LICENSE("GPL");
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