1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * MOXA ART SoCs clock driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Jonas Jensen
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Jonas Jensen <jonas.jensen@gmail.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/clk-provider.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/of_address.h>
17*4882a593Smuzhiyun #include <linux/clkdev.h>
18*4882a593Smuzhiyun
moxart_of_pll_clk_init(struct device_node * node)19*4882a593Smuzhiyun static void __init moxart_of_pll_clk_init(struct device_node *node)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun void __iomem *base;
22*4882a593Smuzhiyun struct clk_hw *hw;
23*4882a593Smuzhiyun struct clk *ref_clk;
24*4882a593Smuzhiyun unsigned int mul;
25*4882a593Smuzhiyun const char *name = node->name;
26*4882a593Smuzhiyun const char *parent_name;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &name);
29*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(node, 0);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun base = of_iomap(node, 0);
32*4882a593Smuzhiyun if (!base) {
33*4882a593Smuzhiyun pr_err("%pOF: of_iomap failed\n", node);
34*4882a593Smuzhiyun return;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun mul = readl(base + 0x30) >> 3 & 0x3f;
38*4882a593Smuzhiyun iounmap(base);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ref_clk = of_clk_get(node, 0);
41*4882a593Smuzhiyun if (IS_ERR(ref_clk)) {
42*4882a593Smuzhiyun pr_err("%pOF: of_clk_get failed\n", node);
43*4882a593Smuzhiyun return;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
47*4882a593Smuzhiyun if (IS_ERR(hw)) {
48*4882a593Smuzhiyun pr_err("%pOF: failed to register clock\n", node);
49*4882a593Smuzhiyun return;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun clk_hw_register_clkdev(hw, NULL, name);
53*4882a593Smuzhiyun of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
56*4882a593Smuzhiyun moxart_of_pll_clk_init);
57*4882a593Smuzhiyun
moxart_of_apb_clk_init(struct device_node * node)58*4882a593Smuzhiyun static void __init moxart_of_apb_clk_init(struct device_node *node)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun void __iomem *base;
61*4882a593Smuzhiyun struct clk_hw *hw;
62*4882a593Smuzhiyun struct clk *pll_clk;
63*4882a593Smuzhiyun unsigned int div, val;
64*4882a593Smuzhiyun unsigned int div_idx[] = { 2, 3, 4, 6, 8};
65*4882a593Smuzhiyun const char *name = node->name;
66*4882a593Smuzhiyun const char *parent_name;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &name);
69*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(node, 0);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun base = of_iomap(node, 0);
72*4882a593Smuzhiyun if (!base) {
73*4882a593Smuzhiyun pr_err("%pOF: of_iomap failed\n", node);
74*4882a593Smuzhiyun return;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun val = readl(base + 0xc) >> 4 & 0x7;
78*4882a593Smuzhiyun iounmap(base);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (val > 4)
81*4882a593Smuzhiyun val = 0;
82*4882a593Smuzhiyun div = div_idx[val] * 2;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun pll_clk = of_clk_get(node, 0);
85*4882a593Smuzhiyun if (IS_ERR(pll_clk)) {
86*4882a593Smuzhiyun pr_err("%pOF: of_clk_get failed\n", node);
87*4882a593Smuzhiyun return;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
91*4882a593Smuzhiyun if (IS_ERR(hw)) {
92*4882a593Smuzhiyun pr_err("%pOF: failed to register clock\n", node);
93*4882a593Smuzhiyun return;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun clk_hw_register_clkdev(hw, NULL, name);
97*4882a593Smuzhiyun of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock",
100*4882a593Smuzhiyun moxart_of_apb_clk_init);
101