1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Clock driver for Hi655x
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017, Linaro Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Daniel Lezcano <daniel.lezcano@linaro.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/mfd/core.h>
15*4882a593Smuzhiyun #include <linux/mfd/hi655x-pmic.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define HI655X_CLK_BASE HI655X_BUS_ADDR(0x1c)
18*4882a593Smuzhiyun #define HI655X_CLK_SET BIT(6)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct hi655x_clk {
21*4882a593Smuzhiyun struct hi655x_pmic *hi655x;
22*4882a593Smuzhiyun struct clk_hw clk_hw;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
hi655x_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)25*4882a593Smuzhiyun static unsigned long hi655x_clk_recalc_rate(struct clk_hw *hw,
26*4882a593Smuzhiyun unsigned long parent_rate)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun return 32768;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
hi655x_clk_enable(struct clk_hw * hw,bool enable)31*4882a593Smuzhiyun static int hi655x_clk_enable(struct clk_hw *hw, bool enable)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct hi655x_clk *hi655x_clk =
34*4882a593Smuzhiyun container_of(hw, struct hi655x_clk, clk_hw);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return regmap_update_bits(hi655x->regmap, HI655X_CLK_BASE,
39*4882a593Smuzhiyun HI655X_CLK_SET, enable ? HI655X_CLK_SET : 0);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
hi655x_clk_prepare(struct clk_hw * hw)42*4882a593Smuzhiyun static int hi655x_clk_prepare(struct clk_hw *hw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun return hi655x_clk_enable(hw, true);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
hi655x_clk_unprepare(struct clk_hw * hw)47*4882a593Smuzhiyun static void hi655x_clk_unprepare(struct clk_hw *hw)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun hi655x_clk_enable(hw, false);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
hi655x_clk_is_prepared(struct clk_hw * hw)52*4882a593Smuzhiyun static int hi655x_clk_is_prepared(struct clk_hw *hw)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct hi655x_clk *hi655x_clk =
55*4882a593Smuzhiyun container_of(hw, struct hi655x_clk, clk_hw);
56*4882a593Smuzhiyun struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
57*4882a593Smuzhiyun int ret;
58*4882a593Smuzhiyun uint32_t val;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = regmap_read(hi655x->regmap, HI655X_CLK_BASE, &val);
61*4882a593Smuzhiyun if (ret < 0)
62*4882a593Smuzhiyun return ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return val & HI655X_CLK_BASE;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct clk_ops hi655x_clk_ops = {
68*4882a593Smuzhiyun .prepare = hi655x_clk_prepare,
69*4882a593Smuzhiyun .unprepare = hi655x_clk_unprepare,
70*4882a593Smuzhiyun .is_prepared = hi655x_clk_is_prepared,
71*4882a593Smuzhiyun .recalc_rate = hi655x_clk_recalc_rate,
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
hi655x_clk_probe(struct platform_device * pdev)74*4882a593Smuzhiyun static int hi655x_clk_probe(struct platform_device *pdev)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct device *parent = pdev->dev.parent;
77*4882a593Smuzhiyun struct hi655x_pmic *hi655x = dev_get_drvdata(parent);
78*4882a593Smuzhiyun struct hi655x_clk *hi655x_clk;
79*4882a593Smuzhiyun const char *clk_name = "hi655x-clk";
80*4882a593Smuzhiyun struct clk_init_data init = {
81*4882a593Smuzhiyun .name = clk_name,
82*4882a593Smuzhiyun .ops = &hi655x_clk_ops
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun int ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
87*4882a593Smuzhiyun if (!hi655x_clk)
88*4882a593Smuzhiyun return -ENOMEM;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun of_property_read_string_index(parent->of_node, "clock-output-names",
91*4882a593Smuzhiyun 0, &clk_name);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun hi655x_clk->clk_hw.init = &init;
94*4882a593Smuzhiyun hi655x_clk->hi655x = hi655x;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun platform_set_drvdata(pdev, hi655x_clk);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
99*4882a593Smuzhiyun if (ret)
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
103*4882a593Smuzhiyun &hi655x_clk->clk_hw);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static struct platform_driver hi655x_clk_driver = {
107*4882a593Smuzhiyun .probe = hi655x_clk_probe,
108*4882a593Smuzhiyun .driver = {
109*4882a593Smuzhiyun .name = "hi655x-clk",
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun module_platform_driver(hi655x_clk_driver);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun MODULE_DESCRIPTION("Clk driver for the hi655x series PMICs");
116*4882a593Smuzhiyun MODULE_AUTHOR("Daniel Lezcano <daniel.lezcano@linaro.org>");
117*4882a593Smuzhiyun MODULE_LICENSE("GPL");
118*4882a593Smuzhiyun MODULE_ALIAS("platform:hi655x-clk");
119