1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Freescale SAI BCLK as a generic clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2020 Michael Walle <michael@walle.cc>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define I2S_CSR 0x00
17*4882a593Smuzhiyun #define I2S_CR2 0x08
18*4882a593Smuzhiyun #define CSR_BCE_BIT 28
19*4882a593Smuzhiyun #define CR2_BCD BIT(24)
20*4882a593Smuzhiyun #define CR2_DIV_SHIFT 0
21*4882a593Smuzhiyun #define CR2_DIV_WIDTH 8
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct fsl_sai_clk {
24*4882a593Smuzhiyun struct clk_divider div;
25*4882a593Smuzhiyun struct clk_gate gate;
26*4882a593Smuzhiyun spinlock_t lock;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
fsl_sai_clk_probe(struct platform_device * pdev)29*4882a593Smuzhiyun static int fsl_sai_clk_probe(struct platform_device *pdev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct device *dev = &pdev->dev;
32*4882a593Smuzhiyun struct fsl_sai_clk *sai_clk;
33*4882a593Smuzhiyun struct clk_parent_data pdata = { .index = 0 };
34*4882a593Smuzhiyun void __iomem *base;
35*4882a593Smuzhiyun struct clk_hw *hw;
36*4882a593Smuzhiyun struct resource *res;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
39*4882a593Smuzhiyun if (!sai_clk)
40*4882a593Smuzhiyun return -ENOMEM;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
43*4882a593Smuzhiyun base = devm_ioremap_resource(dev, res);
44*4882a593Smuzhiyun if (IS_ERR(base))
45*4882a593Smuzhiyun return PTR_ERR(base);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun spin_lock_init(&sai_clk->lock);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun sai_clk->gate.reg = base + I2S_CSR;
50*4882a593Smuzhiyun sai_clk->gate.bit_idx = CSR_BCE_BIT;
51*4882a593Smuzhiyun sai_clk->gate.lock = &sai_clk->lock;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun sai_clk->div.reg = base + I2S_CR2;
54*4882a593Smuzhiyun sai_clk->div.shift = CR2_DIV_SHIFT;
55*4882a593Smuzhiyun sai_clk->div.width = CR2_DIV_WIDTH;
56*4882a593Smuzhiyun sai_clk->div.lock = &sai_clk->lock;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* set clock direction, we are the BCLK master */
59*4882a593Smuzhiyun writel(CR2_BCD, base + I2S_CR2);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun hw = clk_hw_register_composite_pdata(dev, dev->of_node->name,
62*4882a593Smuzhiyun &pdata, 1, NULL, NULL,
63*4882a593Smuzhiyun &sai_clk->div.hw,
64*4882a593Smuzhiyun &clk_divider_ops,
65*4882a593Smuzhiyun &sai_clk->gate.hw,
66*4882a593Smuzhiyun &clk_gate_ops,
67*4882a593Smuzhiyun CLK_SET_RATE_GATE);
68*4882a593Smuzhiyun if (IS_ERR(hw))
69*4882a593Smuzhiyun return PTR_ERR(hw);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun platform_set_drvdata(pdev, hw);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
fsl_sai_clk_remove(struct platform_device * pdev)76*4882a593Smuzhiyun static int fsl_sai_clk_remove(struct platform_device *pdev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct clk_hw *hw = platform_get_drvdata(pdev);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun clk_hw_unregister_composite(hw);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct of_device_id of_fsl_sai_clk_ids[] = {
86*4882a593Smuzhiyun { .compatible = "fsl,vf610-sai-clock" },
87*4882a593Smuzhiyun { }
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static struct platform_driver fsl_sai_clk_driver = {
92*4882a593Smuzhiyun .probe = fsl_sai_clk_probe,
93*4882a593Smuzhiyun .remove = fsl_sai_clk_remove,
94*4882a593Smuzhiyun .driver = {
95*4882a593Smuzhiyun .name = "fsl-sai-clk",
96*4882a593Smuzhiyun .of_match_table = of_fsl_sai_clk_ids,
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun module_platform_driver(fsl_sai_clk_driver);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
102*4882a593Smuzhiyun MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
103*4882a593Smuzhiyun MODULE_LICENSE("GPL");
104*4882a593Smuzhiyun MODULE_ALIAS("platform:fsl-sai-clk");
105