1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Structures used by ASPEED clock drivers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2019 IBM Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/clk-provider.h> 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun #include <linux/reset-controller.h> 11*4882a593Smuzhiyun #include <linux/spinlock.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct clk_div_table; 14*4882a593Smuzhiyun struct regmap; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /** 17*4882a593Smuzhiyun * struct aspeed_gate_data - Aspeed gated clocks 18*4882a593Smuzhiyun * @clock_idx: bit used to gate this clock in the clock register 19*4882a593Smuzhiyun * @reset_idx: bit used to reset this IP in the reset register. -1 if no 20*4882a593Smuzhiyun * reset is required when enabling the clock 21*4882a593Smuzhiyun * @name: the clock name 22*4882a593Smuzhiyun * @parent_name: the name of the parent clock 23*4882a593Smuzhiyun * @flags: standard clock framework flags 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun struct aspeed_gate_data { 26*4882a593Smuzhiyun u8 clock_idx; 27*4882a593Smuzhiyun s8 reset_idx; 28*4882a593Smuzhiyun const char *name; 29*4882a593Smuzhiyun const char *parent_name; 30*4882a593Smuzhiyun unsigned long flags; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /** 34*4882a593Smuzhiyun * struct aspeed_clk_gate - Aspeed specific clk_gate structure 35*4882a593Smuzhiyun * @hw: handle between common and hardware-specific interfaces 36*4882a593Smuzhiyun * @reg: register controlling gate 37*4882a593Smuzhiyun * @clock_idx: bit used to gate this clock in the clock register 38*4882a593Smuzhiyun * @reset_idx: bit used to reset this IP in the reset register. -1 if no 39*4882a593Smuzhiyun * reset is required when enabling the clock 40*4882a593Smuzhiyun * @flags: hardware-specific flags 41*4882a593Smuzhiyun * @lock: register lock 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * Some of the clocks in the Aspeed SoC must be put in reset before enabling. 44*4882a593Smuzhiyun * This modified version of clk_gate allows an optional reset bit to be 45*4882a593Smuzhiyun * specified. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct aspeed_clk_gate { 48*4882a593Smuzhiyun struct clk_hw hw; 49*4882a593Smuzhiyun struct regmap *map; 50*4882a593Smuzhiyun u8 clock_idx; 51*4882a593Smuzhiyun s8 reset_idx; 52*4882a593Smuzhiyun u8 flags; 53*4882a593Smuzhiyun spinlock_t *lock; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /** 59*4882a593Smuzhiyun * struct aspeed_reset - Aspeed reset controller 60*4882a593Smuzhiyun * @map: regmap to access the containing system controller 61*4882a593Smuzhiyun * @rcdev: reset controller device 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun struct aspeed_reset { 64*4882a593Smuzhiyun struct regmap *map; 65*4882a593Smuzhiyun struct reset_controller_dev rcdev; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /** 71*4882a593Smuzhiyun * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information 72*4882a593Smuzhiyun * @div_table: Common divider lookup table 73*4882a593Smuzhiyun * @eclk_div_table: Divider lookup table for ECLK 74*4882a593Smuzhiyun * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks 75*4882a593Smuzhiyun * @calc_pll: Callback to maculate common PLL settings 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun struct aspeed_clk_soc_data { 78*4882a593Smuzhiyun const struct clk_div_table *div_table; 79*4882a593Smuzhiyun const struct clk_div_table *eclk_div_table; 80*4882a593Smuzhiyun const struct clk_div_table *mac_div_table; 81*4882a593Smuzhiyun struct clk_hw *(*calc_pll)(const char *name, u32 val); 82*4882a593Smuzhiyun }; 83