1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define PMU_XTAL_FREQ_RATIO 0x66c
16*4882a593Smuzhiyun #define XTAL_ALP_PER_4ILP 0x00001fff
17*4882a593Smuzhiyun #define XTAL_CTL_EN 0x80000000
18*4882a593Smuzhiyun #define PMU_SLOW_CLK_PERIOD 0x6dc
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct bcm53573_ilp {
21*4882a593Smuzhiyun struct clk_hw hw;
22*4882a593Smuzhiyun struct regmap *regmap;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
bcm53573_ilp_enable(struct clk_hw * hw)25*4882a593Smuzhiyun static int bcm53573_ilp_enable(struct clk_hw *hw)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0x10199);
30*4882a593Smuzhiyun regmap_write(ilp->regmap, 0x674, 0x10000);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return 0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
bcm53573_ilp_disable(struct clk_hw * hw)35*4882a593Smuzhiyun static void bcm53573_ilp_disable(struct clk_hw *hw)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0);
40*4882a593Smuzhiyun regmap_write(ilp->regmap, 0x674, 0);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
bcm53573_ilp_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)43*4882a593Smuzhiyun static unsigned long bcm53573_ilp_recalc_rate(struct clk_hw *hw,
44*4882a593Smuzhiyun unsigned long parent_rate)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
47*4882a593Smuzhiyun struct regmap *regmap = ilp->regmap;
48*4882a593Smuzhiyun u32 last_val, cur_val;
49*4882a593Smuzhiyun int sum = 0, num = 0, loop_num = 0;
50*4882a593Smuzhiyun int avg;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Enable measurement */
53*4882a593Smuzhiyun regmap_write(regmap, PMU_XTAL_FREQ_RATIO, XTAL_CTL_EN);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Read initial value */
56*4882a593Smuzhiyun regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &last_val);
57*4882a593Smuzhiyun last_val &= XTAL_ALP_PER_4ILP;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * At minimum we should loop for a bit to let hardware do the
61*4882a593Smuzhiyun * measurement. This isn't very accurate however, so for a better
62*4882a593Smuzhiyun * precision lets try getting 20 different values for and use average.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun while (num < 20) {
65*4882a593Smuzhiyun regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &cur_val);
66*4882a593Smuzhiyun cur_val &= XTAL_ALP_PER_4ILP;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (cur_val != last_val) {
69*4882a593Smuzhiyun /* Got different value, use it */
70*4882a593Smuzhiyun sum += cur_val;
71*4882a593Smuzhiyun num++;
72*4882a593Smuzhiyun loop_num = 0;
73*4882a593Smuzhiyun last_val = cur_val;
74*4882a593Smuzhiyun } else if (++loop_num > 5000) {
75*4882a593Smuzhiyun /* Same value over and over, give up */
76*4882a593Smuzhiyun sum += cur_val;
77*4882a593Smuzhiyun num++;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun cpu_relax();
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Disable measurement to save power */
85*4882a593Smuzhiyun regmap_write(regmap, PMU_XTAL_FREQ_RATIO, 0x0);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun avg = sum / num;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return parent_rate * 4 / avg;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static const struct clk_ops bcm53573_ilp_clk_ops = {
93*4882a593Smuzhiyun .enable = bcm53573_ilp_enable,
94*4882a593Smuzhiyun .disable = bcm53573_ilp_disable,
95*4882a593Smuzhiyun .recalc_rate = bcm53573_ilp_recalc_rate,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
bcm53573_ilp_init(struct device_node * np)98*4882a593Smuzhiyun static void bcm53573_ilp_init(struct device_node *np)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct bcm53573_ilp *ilp;
101*4882a593Smuzhiyun struct clk_init_data init = { };
102*4882a593Smuzhiyun const char *parent_name;
103*4882a593Smuzhiyun int err;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ilp = kzalloc(sizeof(*ilp), GFP_KERNEL);
106*4882a593Smuzhiyun if (!ilp)
107*4882a593Smuzhiyun return;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(np, 0);
110*4882a593Smuzhiyun if (!parent_name) {
111*4882a593Smuzhiyun err = -ENOENT;
112*4882a593Smuzhiyun goto err_free_ilp;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ilp->regmap = syscon_node_to_regmap(of_get_parent(np));
116*4882a593Smuzhiyun if (IS_ERR(ilp->regmap)) {
117*4882a593Smuzhiyun err = PTR_ERR(ilp->regmap);
118*4882a593Smuzhiyun goto err_free_ilp;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun init.name = np->name;
122*4882a593Smuzhiyun init.ops = &bcm53573_ilp_clk_ops;
123*4882a593Smuzhiyun init.parent_names = &parent_name;
124*4882a593Smuzhiyun init.num_parents = 1;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun ilp->hw.init = &init;
127*4882a593Smuzhiyun err = clk_hw_register(NULL, &ilp->hw);
128*4882a593Smuzhiyun if (err)
129*4882a593Smuzhiyun goto err_free_ilp;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun err = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &ilp->hw);
132*4882a593Smuzhiyun if (err)
133*4882a593Smuzhiyun goto err_clk_hw_unregister;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun err_clk_hw_unregister:
138*4882a593Smuzhiyun clk_hw_unregister(&ilp->hw);
139*4882a593Smuzhiyun err_free_ilp:
140*4882a593Smuzhiyun kfree(ilp);
141*4882a593Smuzhiyun pr_err("Failed to init ILP clock: %d\n", err);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* We need it very early for arch code, before device model gets ready */
145*4882a593Smuzhiyun CLK_OF_DECLARE(bcm53573_ilp_clk, "brcm,bcm53573-ilp", bcm53573_ilp_init);
146