1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun // Copyright 2020 Cerno
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/clk-provider.h>
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/platform_device.h>
7*4882a593Smuzhiyun #include <linux/reset-controller.h>
8*4882a593Smuzhiyun #include <linux/reset/reset-simple.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define DVP_HT_RPI_SW_INIT 0x04
11*4882a593Smuzhiyun #define DVP_HT_RPI_MISC_CONFIG 0x08
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define NR_CLOCKS 2
14*4882a593Smuzhiyun #define NR_RESETS 6
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct clk_dvp {
17*4882a593Smuzhiyun struct clk_hw_onecell_data *data;
18*4882a593Smuzhiyun struct reset_simple_data reset;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct clk_parent_data clk_dvp_parent = {
22*4882a593Smuzhiyun .index = 0,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
clk_dvp_probe(struct platform_device * pdev)25*4882a593Smuzhiyun static int clk_dvp_probe(struct platform_device *pdev)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct clk_hw_onecell_data *data;
28*4882a593Smuzhiyun struct resource *res;
29*4882a593Smuzhiyun struct clk_dvp *dvp;
30*4882a593Smuzhiyun void __iomem *base;
31*4882a593Smuzhiyun int ret;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL);
34*4882a593Smuzhiyun if (!dvp)
35*4882a593Smuzhiyun return -ENOMEM;
36*4882a593Smuzhiyun platform_set_drvdata(pdev, dvp);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun dvp->data = devm_kzalloc(&pdev->dev,
39*4882a593Smuzhiyun struct_size(dvp->data, hws, NR_CLOCKS),
40*4882a593Smuzhiyun GFP_KERNEL);
41*4882a593Smuzhiyun if (!dvp->data)
42*4882a593Smuzhiyun return -ENOMEM;
43*4882a593Smuzhiyun data = dvp->data;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
46*4882a593Smuzhiyun if (IS_ERR(base))
47*4882a593Smuzhiyun return PTR_ERR(base);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun dvp->reset.rcdev.owner = THIS_MODULE;
50*4882a593Smuzhiyun dvp->reset.rcdev.nr_resets = NR_RESETS;
51*4882a593Smuzhiyun dvp->reset.rcdev.ops = &reset_simple_ops;
52*4882a593Smuzhiyun dvp->reset.rcdev.of_node = pdev->dev.of_node;
53*4882a593Smuzhiyun dvp->reset.membase = base + DVP_HT_RPI_SW_INIT;
54*4882a593Smuzhiyun spin_lock_init(&dvp->reset.lock);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun ret = devm_reset_controller_register(&pdev->dev, &dvp->reset.rcdev);
57*4882a593Smuzhiyun if (ret)
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
61*4882a593Smuzhiyun "hdmi0-108MHz",
62*4882a593Smuzhiyun &clk_dvp_parent, 0,
63*4882a593Smuzhiyun base + DVP_HT_RPI_MISC_CONFIG, 3,
64*4882a593Smuzhiyun CLK_GATE_SET_TO_DISABLE,
65*4882a593Smuzhiyun &dvp->reset.lock);
66*4882a593Smuzhiyun if (IS_ERR(data->hws[0]))
67*4882a593Smuzhiyun return PTR_ERR(data->hws[0]);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev,
70*4882a593Smuzhiyun "hdmi1-108MHz",
71*4882a593Smuzhiyun &clk_dvp_parent, 0,
72*4882a593Smuzhiyun base + DVP_HT_RPI_MISC_CONFIG, 4,
73*4882a593Smuzhiyun CLK_GATE_SET_TO_DISABLE,
74*4882a593Smuzhiyun &dvp->reset.lock);
75*4882a593Smuzhiyun if (IS_ERR(data->hws[1])) {
76*4882a593Smuzhiyun ret = PTR_ERR(data->hws[1]);
77*4882a593Smuzhiyun goto unregister_clk0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun data->num = NR_CLOCKS;
81*4882a593Smuzhiyun ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
82*4882a593Smuzhiyun data);
83*4882a593Smuzhiyun if (ret)
84*4882a593Smuzhiyun goto unregister_clk1;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun unregister_clk1:
89*4882a593Smuzhiyun clk_hw_unregister_gate(data->hws[1]);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun unregister_clk0:
92*4882a593Smuzhiyun clk_hw_unregister_gate(data->hws[0]);
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
clk_dvp_remove(struct platform_device * pdev)96*4882a593Smuzhiyun static int clk_dvp_remove(struct platform_device *pdev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct clk_dvp *dvp = platform_get_drvdata(pdev);
99*4882a593Smuzhiyun struct clk_hw_onecell_data *data = dvp->data;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun clk_hw_unregister_gate(data->hws[1]);
102*4882a593Smuzhiyun clk_hw_unregister_gate(data->hws[0]);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const struct of_device_id clk_dvp_dt_ids[] = {
108*4882a593Smuzhiyun { .compatible = "brcm,brcm2711-dvp", },
109*4882a593Smuzhiyun { /* sentinel */ }
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, clk_dvp_dt_ids);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static struct platform_driver clk_dvp_driver = {
114*4882a593Smuzhiyun .probe = clk_dvp_probe,
115*4882a593Smuzhiyun .remove = clk_dvp_remove,
116*4882a593Smuzhiyun .driver = {
117*4882a593Smuzhiyun .name = "brcm2711-dvp",
118*4882a593Smuzhiyun .of_match_table = clk_dvp_dt_ids,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun module_platform_driver(clk_dvp_driver);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>");
124*4882a593Smuzhiyun MODULE_DESCRIPTION("BCM2711 DVP clock driver");
125*4882a593Smuzhiyun MODULE_LICENSE("GPL");
126