1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Baikal-T1 CCU PLL interface driver 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __CLK_BT1_CCU_PLL_H__ 8*4882a593Smuzhiyun #define __CLK_BT1_CCU_PLL_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/clk-provider.h> 11*4882a593Smuzhiyun #include <linux/spinlock.h> 12*4882a593Smuzhiyun #include <linux/regmap.h> 13*4882a593Smuzhiyun #include <linux/bits.h> 14*4882a593Smuzhiyun #include <linux/of.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * struct ccu_pll_init_data - CCU PLL initialization data 18*4882a593Smuzhiyun * @id: Clock private identifier. 19*4882a593Smuzhiyun * @name: Clocks name. 20*4882a593Smuzhiyun * @parent_name: Clocks parent name in a fw node. 21*4882a593Smuzhiyun * @base: PLL registers base address with respect to the sys_regs base. 22*4882a593Smuzhiyun * @sys_regs: Baikal-T1 System Controller registers map. 23*4882a593Smuzhiyun * @np: Pointer to the node describing the CCU PLLs. 24*4882a593Smuzhiyun * @flags: PLL clock flags. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun struct ccu_pll_init_data { 27*4882a593Smuzhiyun unsigned int id; 28*4882a593Smuzhiyun const char *name; 29*4882a593Smuzhiyun const char *parent_name; 30*4882a593Smuzhiyun unsigned int base; 31*4882a593Smuzhiyun struct regmap *sys_regs; 32*4882a593Smuzhiyun struct device_node *np; 33*4882a593Smuzhiyun unsigned long flags; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * struct ccu_pll - CCU PLL descriptor 38*4882a593Smuzhiyun * @hw: clk_hw of the PLL. 39*4882a593Smuzhiyun * @id: Clock private identifier. 40*4882a593Smuzhiyun * @reg_ctl: PLL control register base. 41*4882a593Smuzhiyun * @reg_ctl1: PLL control1 register base. 42*4882a593Smuzhiyun * @sys_regs: Baikal-T1 System Controller registers map. 43*4882a593Smuzhiyun * @lock: PLL state change spin-lock. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun struct ccu_pll { 46*4882a593Smuzhiyun struct clk_hw hw; 47*4882a593Smuzhiyun unsigned int id; 48*4882a593Smuzhiyun unsigned int reg_ctl; 49*4882a593Smuzhiyun unsigned int reg_ctl1; 50*4882a593Smuzhiyun struct regmap *sys_regs; 51*4882a593Smuzhiyun spinlock_t lock; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun #define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw) 54*4882a593Smuzhiyun ccu_pll_get_clk_hw(struct ccu_pll * pll)55*4882a593Smuzhiyunstatic inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun return pll ? &pll->hw : NULL; 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun void ccu_pll_hw_unregister(struct ccu_pll *pll); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __CLK_BT1_CCU_PLL_H__ */ 65