1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunconfig CLK_BAIKAL_T1 3*4882a593Smuzhiyun bool "Baikal-T1 Clocks Control Unit interface" 4*4882a593Smuzhiyun depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST 5*4882a593Smuzhiyun default MIPS_BAIKAL_T1 6*4882a593Smuzhiyun help 7*4882a593Smuzhiyun Clocks Control Unit is the core of Baikal-T1 SoC System Controller 8*4882a593Smuzhiyun responsible for the chip subsystems clocking and resetting. It 9*4882a593Smuzhiyun consists of multiple global clock domains, which can be reset by 10*4882a593Smuzhiyun means of the CCU control registers. These domains and devices placed 11*4882a593Smuzhiyun in them are fed with clocks generated by a hierarchy of PLLs, 12*4882a593Smuzhiyun configurable and fixed clock dividers. Enable this option to be able 13*4882a593Smuzhiyun to select Baikal-T1 CCU PLLs and Dividers drivers. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunif CLK_BAIKAL_T1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunconfig CLK_BT1_CCU_PLL 18*4882a593Smuzhiyun bool "Baikal-T1 CCU PLLs support" 19*4882a593Smuzhiyun select MFD_SYSCON 20*4882a593Smuzhiyun default MIPS_BAIKAL_T1 21*4882a593Smuzhiyun help 22*4882a593Smuzhiyun Enable this to support the PLLs embedded into the Baikal-T1 SoC 23*4882a593Smuzhiyun System Controller. These are five PLLs placed at the root of the 24*4882a593Smuzhiyun clocks hierarchy, right after an external reference oscillator 25*4882a593Smuzhiyun (normally of 25MHz). They are used to generate high frequency 26*4882a593Smuzhiyun signals, which are either directly wired to the consumers (like 27*4882a593Smuzhiyun CPUs, DDR, etc.) or passed over the clock dividers to be only 28*4882a593Smuzhiyun then used as an individual reference clock of a target device. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunconfig CLK_BT1_CCU_DIV 31*4882a593Smuzhiyun bool "Baikal-T1 CCU Dividers support" 32*4882a593Smuzhiyun select RESET_CONTROLLER 33*4882a593Smuzhiyun select MFD_SYSCON 34*4882a593Smuzhiyun default MIPS_BAIKAL_T1 35*4882a593Smuzhiyun help 36*4882a593Smuzhiyun Enable this to support the CCU dividers used to distribute clocks 37*4882a593Smuzhiyun between AXI-bus and system devices coming from CCU PLLs of Baikal-T1 38*4882a593Smuzhiyun SoC. CCU dividers can be either configurable or with fixed divider, 39*4882a593Smuzhiyun either gateable or ungateable. Some of the CCU dividers can be as well 40*4882a593Smuzhiyun used to reset the domains they're supplying clock to. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunendif 43