1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/clkdev.h>
8*4882a593Smuzhiyun #include <linux/clk/at91_pmc.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/syscore_ops.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/proc-fns.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <dt-bindings/clock/at91.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "pmc.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define PMC_MAX_IDS 128
22*4882a593Smuzhiyun #define PMC_MAX_PCKS 8
23*4882a593Smuzhiyun
of_at91_get_clk_range(struct device_node * np,const char * propname,struct clk_range * range)24*4882a593Smuzhiyun int of_at91_get_clk_range(struct device_node *np, const char *propname,
25*4882a593Smuzhiyun struct clk_range *range)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun u32 min, max;
28*4882a593Smuzhiyun int ret;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun ret = of_property_read_u32_index(np, propname, 0, &min);
31*4882a593Smuzhiyun if (ret)
32*4882a593Smuzhiyun return ret;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun ret = of_property_read_u32_index(np, propname, 1, &max);
35*4882a593Smuzhiyun if (ret)
36*4882a593Smuzhiyun return ret;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun if (range) {
39*4882a593Smuzhiyun range->min = min;
40*4882a593Smuzhiyun range->max = max;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
46*4882a593Smuzhiyun
of_clk_hw_pmc_get(struct of_phandle_args * clkspec,void * data)47*4882a593Smuzhiyun struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun unsigned int type = clkspec->args[0];
50*4882a593Smuzhiyun unsigned int idx = clkspec->args[1];
51*4882a593Smuzhiyun struct pmc_data *pmc_data = data;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun switch (type) {
54*4882a593Smuzhiyun case PMC_TYPE_CORE:
55*4882a593Smuzhiyun if (idx < pmc_data->ncore)
56*4882a593Smuzhiyun return pmc_data->chws[idx];
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case PMC_TYPE_SYSTEM:
59*4882a593Smuzhiyun if (idx < pmc_data->nsystem)
60*4882a593Smuzhiyun return pmc_data->shws[idx];
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun case PMC_TYPE_PERIPHERAL:
63*4882a593Smuzhiyun if (idx < pmc_data->nperiph)
64*4882a593Smuzhiyun return pmc_data->phws[idx];
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun case PMC_TYPE_GCK:
67*4882a593Smuzhiyun if (idx < pmc_data->ngck)
68*4882a593Smuzhiyun return pmc_data->ghws[idx];
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun case PMC_TYPE_PROGRAMMABLE:
71*4882a593Smuzhiyun if (idx < pmc_data->npck)
72*4882a593Smuzhiyun return pmc_data->pchws[idx];
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun default:
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
pmc_data_allocate(unsigned int ncore,unsigned int nsystem,unsigned int nperiph,unsigned int ngck,unsigned int npck)83*4882a593Smuzhiyun struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
84*4882a593Smuzhiyun unsigned int nperiph, unsigned int ngck,
85*4882a593Smuzhiyun unsigned int npck)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck;
88*4882a593Smuzhiyun struct pmc_data *pmc_data;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks),
91*4882a593Smuzhiyun GFP_KERNEL);
92*4882a593Smuzhiyun if (!pmc_data)
93*4882a593Smuzhiyun return NULL;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun pmc_data->ncore = ncore;
96*4882a593Smuzhiyun pmc_data->chws = pmc_data->hwtable;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun pmc_data->nsystem = nsystem;
99*4882a593Smuzhiyun pmc_data->shws = pmc_data->chws + ncore;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun pmc_data->nperiph = nperiph;
102*4882a593Smuzhiyun pmc_data->phws = pmc_data->shws + nsystem;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun pmc_data->ngck = ngck;
105*4882a593Smuzhiyun pmc_data->ghws = pmc_data->phws + nperiph;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun pmc_data->npck = npck;
108*4882a593Smuzhiyun pmc_data->pchws = pmc_data->ghws + ngck;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return pmc_data;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #ifdef CONFIG_PM
114*4882a593Smuzhiyun static struct regmap *pmcreg;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static u8 registered_ids[PMC_MAX_IDS];
117*4882a593Smuzhiyun static u8 registered_pcks[PMC_MAX_PCKS];
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static struct
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun u32 scsr;
122*4882a593Smuzhiyun u32 pcsr0;
123*4882a593Smuzhiyun u32 uckr;
124*4882a593Smuzhiyun u32 mor;
125*4882a593Smuzhiyun u32 mcfr;
126*4882a593Smuzhiyun u32 pllar;
127*4882a593Smuzhiyun u32 mckr;
128*4882a593Smuzhiyun u32 usb;
129*4882a593Smuzhiyun u32 imr;
130*4882a593Smuzhiyun u32 pcsr1;
131*4882a593Smuzhiyun u32 pcr[PMC_MAX_IDS];
132*4882a593Smuzhiyun u32 audio_pll0;
133*4882a593Smuzhiyun u32 audio_pll1;
134*4882a593Smuzhiyun u32 pckr[PMC_MAX_PCKS];
135*4882a593Smuzhiyun } pmc_cache;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
139*4882a593Smuzhiyun * without alteration in the table, and 0 is for unused clocks.
140*4882a593Smuzhiyun */
pmc_register_id(u8 id)141*4882a593Smuzhiyun void pmc_register_id(u8 id)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun int i;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun for (i = 0; i < PMC_MAX_IDS; i++) {
146*4882a593Smuzhiyun if (registered_ids[i] == 0) {
147*4882a593Smuzhiyun registered_ids[i] = id;
148*4882a593Smuzhiyun break;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun if (registered_ids[i] == id)
151*4882a593Smuzhiyun break;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun * As Programmable Clock 0 is valid on AT91 chips, there is an offset
157*4882a593Smuzhiyun * of 1 between the stored value and the real clock ID.
158*4882a593Smuzhiyun */
pmc_register_pck(u8 pck)159*4882a593Smuzhiyun void pmc_register_pck(u8 pck)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun int i;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun for (i = 0; i < PMC_MAX_PCKS; i++) {
164*4882a593Smuzhiyun if (registered_pcks[i] == 0) {
165*4882a593Smuzhiyun registered_pcks[i] = pck + 1;
166*4882a593Smuzhiyun break;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun if (registered_pcks[i] == (pck + 1))
169*4882a593Smuzhiyun break;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
pmc_suspend(void)173*4882a593Smuzhiyun static int pmc_suspend(void)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun int i;
176*4882a593Smuzhiyun u8 num;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
179*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
180*4882a593Smuzhiyun regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
181*4882a593Smuzhiyun regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
182*4882a593Smuzhiyun regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
183*4882a593Smuzhiyun regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
184*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
185*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
186*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
187*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun for (i = 0; registered_ids[i]; i++) {
190*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_PCR,
191*4882a593Smuzhiyun (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
192*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_PCR,
193*4882a593Smuzhiyun &pmc_cache.pcr[registered_ids[i]]);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun for (i = 0; registered_pcks[i]; i++) {
196*4882a593Smuzhiyun num = registered_pcks[i] - 1;
197*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
pmc_ready(unsigned int mask)203*4882a593Smuzhiyun static bool pmc_ready(unsigned int mask)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun unsigned int status;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_SR, &status);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return ((status & mask) == mask) ? 1 : 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
pmc_resume(void)212*4882a593Smuzhiyun static void pmc_resume(void)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun int i;
215*4882a593Smuzhiyun u8 num;
216*4882a593Smuzhiyun u32 tmp;
217*4882a593Smuzhiyun u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
220*4882a593Smuzhiyun if (pmc_cache.mckr != tmp)
221*4882a593Smuzhiyun pr_warn("MCKR was not configured properly by the firmware\n");
222*4882a593Smuzhiyun regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
223*4882a593Smuzhiyun if (pmc_cache.pllar != tmp)
224*4882a593Smuzhiyun pr_warn("PLLAR was not configured properly by the firmware\n");
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
227*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
228*4882a593Smuzhiyun regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
229*4882a593Smuzhiyun regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
230*4882a593Smuzhiyun regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
231*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
232*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
233*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun for (i = 0; registered_ids[i]; i++) {
236*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_PCR,
237*4882a593Smuzhiyun pmc_cache.pcr[registered_ids[i]] |
238*4882a593Smuzhiyun AT91_PMC_PCR_CMD);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun for (i = 0; registered_pcks[i]; i++) {
241*4882a593Smuzhiyun num = registered_pcks[i] - 1;
242*4882a593Smuzhiyun regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (pmc_cache.uckr & AT91_PMC_UPLLEN)
246*4882a593Smuzhiyun mask |= AT91_PMC_LOCKU;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun while (!pmc_ready(mask))
249*4882a593Smuzhiyun cpu_relax();
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct syscore_ops pmc_syscore_ops = {
253*4882a593Smuzhiyun .suspend = pmc_suspend,
254*4882a593Smuzhiyun .resume = pmc_resume,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static const struct of_device_id sama5d2_pmc_dt_ids[] = {
258*4882a593Smuzhiyun { .compatible = "atmel,sama5d2-pmc" },
259*4882a593Smuzhiyun { /* sentinel */ }
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
pmc_register_ops(void)262*4882a593Smuzhiyun static int __init pmc_register_ops(void)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct device_node *np;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
267*4882a593Smuzhiyun if (!np)
268*4882a593Smuzhiyun return -ENODEV;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun if (!of_device_is_available(np)) {
271*4882a593Smuzhiyun of_node_put(np);
272*4882a593Smuzhiyun return -ENODEV;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun pmcreg = device_node_to_regmap(np);
276*4882a593Smuzhiyun of_node_put(np);
277*4882a593Smuzhiyun if (IS_ERR(pmcreg))
278*4882a593Smuzhiyun return PTR_ERR(pmcreg);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun register_syscore_ops(&pmc_syscore_ops);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return 0;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun /* This has to happen before arch_initcall because of the tcb_clksrc driver */
285*4882a593Smuzhiyun postcore_initcall(pmc_register_ops);
286*4882a593Smuzhiyun #endif
287