1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Actions Semi Owl SoCs Reset Management Unit driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd.
6*4882a593Smuzhiyun // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/reset-controller.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "owl-reset.h"
13*4882a593Smuzhiyun
owl_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)14*4882a593Smuzhiyun static int owl_reset_assert(struct reset_controller_dev *rcdev,
15*4882a593Smuzhiyun unsigned long id)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct owl_reset *reset = to_owl_reset(rcdev);
18*4882a593Smuzhiyun const struct owl_reset_map *map = &reset->reset_map[id];
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun return regmap_update_bits(reset->regmap, map->reg, map->bit, 0);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
owl_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)23*4882a593Smuzhiyun static int owl_reset_deassert(struct reset_controller_dev *rcdev,
24*4882a593Smuzhiyun unsigned long id)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct owl_reset *reset = to_owl_reset(rcdev);
27*4882a593Smuzhiyun const struct owl_reset_map *map = &reset->reset_map[id];
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
owl_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)32*4882a593Smuzhiyun static int owl_reset_reset(struct reset_controller_dev *rcdev,
33*4882a593Smuzhiyun unsigned long id)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun owl_reset_assert(rcdev, id);
36*4882a593Smuzhiyun udelay(1);
37*4882a593Smuzhiyun owl_reset_deassert(rcdev, id);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
owl_reset_status(struct reset_controller_dev * rcdev,unsigned long id)42*4882a593Smuzhiyun static int owl_reset_status(struct reset_controller_dev *rcdev,
43*4882a593Smuzhiyun unsigned long id)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct owl_reset *reset = to_owl_reset(rcdev);
46*4882a593Smuzhiyun const struct owl_reset_map *map = &reset->reset_map[id];
47*4882a593Smuzhiyun u32 reg;
48*4882a593Smuzhiyun int ret;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun ret = regmap_read(reset->regmap, map->reg, ®);
51*4882a593Smuzhiyun if (ret)
52*4882a593Smuzhiyun return ret;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * The reset control API expects 0 if reset is not asserted,
56*4882a593Smuzhiyun * which is the opposite of what our hardware uses.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun return !(map->bit & reg);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun const struct reset_control_ops owl_reset_ops = {
62*4882a593Smuzhiyun .assert = owl_reset_assert,
63*4882a593Smuzhiyun .deassert = owl_reset_deassert,
64*4882a593Smuzhiyun .reset = owl_reset_reset,
65*4882a593Smuzhiyun .status = owl_reset_status,
66*4882a593Smuzhiyun };
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