1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // OWL pll clock driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2014 Actions Semi Inc.
6*4882a593Smuzhiyun // Author: David Liu <liuwei@actions-semi.com>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd.
9*4882a593Smuzhiyun // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef _OWL_PLL_H_
12*4882a593Smuzhiyun #define _OWL_PLL_H_
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "owl-common.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define OWL_PLL_DEF_DELAY 50
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* last entry should have rate = 0 */
19*4882a593Smuzhiyun struct clk_pll_table {
20*4882a593Smuzhiyun unsigned int val;
21*4882a593Smuzhiyun unsigned long rate;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct owl_pll_hw {
25*4882a593Smuzhiyun u32 reg;
26*4882a593Smuzhiyun u32 bfreq;
27*4882a593Smuzhiyun u8 bit_idx;
28*4882a593Smuzhiyun u8 shift;
29*4882a593Smuzhiyun u8 width;
30*4882a593Smuzhiyun u8 min_mul;
31*4882a593Smuzhiyun u8 max_mul;
32*4882a593Smuzhiyun u8 delay;
33*4882a593Smuzhiyun const struct clk_pll_table *table;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct owl_pll {
37*4882a593Smuzhiyun struct owl_pll_hw pll_hw;
38*4882a593Smuzhiyun struct owl_clk_common common;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
42*4882a593Smuzhiyun _width, _min_mul, _max_mul, _delay, _table) \
43*4882a593Smuzhiyun { \
44*4882a593Smuzhiyun .reg = _reg, \
45*4882a593Smuzhiyun .bfreq = _bfreq, \
46*4882a593Smuzhiyun .bit_idx = _bit_idx, \
47*4882a593Smuzhiyun .shift = _shift, \
48*4882a593Smuzhiyun .width = _width, \
49*4882a593Smuzhiyun .min_mul = _min_mul, \
50*4882a593Smuzhiyun .max_mul = _max_mul, \
51*4882a593Smuzhiyun .delay = _delay, \
52*4882a593Smuzhiyun .table = _table, \
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
56*4882a593Smuzhiyun _shift, _width, _min_mul, _max_mul, _table, _flags) \
57*4882a593Smuzhiyun struct owl_pll _struct = { \
58*4882a593Smuzhiyun .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
59*4882a593Smuzhiyun _width, _min_mul, _max_mul, \
60*4882a593Smuzhiyun OWL_PLL_DEF_DELAY, _table), \
61*4882a593Smuzhiyun .common = { \
62*4882a593Smuzhiyun .regmap = NULL, \
63*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
64*4882a593Smuzhiyun _parent, \
65*4882a593Smuzhiyun &owl_pll_ops, \
66*4882a593Smuzhiyun _flags), \
67*4882a593Smuzhiyun }, \
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
71*4882a593Smuzhiyun _shift, _width, _min_mul, _max_mul, _table, _flags) \
72*4882a593Smuzhiyun struct owl_pll _struct = { \
73*4882a593Smuzhiyun .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
74*4882a593Smuzhiyun _width, _min_mul, _max_mul, \
75*4882a593Smuzhiyun OWL_PLL_DEF_DELAY, _table), \
76*4882a593Smuzhiyun .common = { \
77*4882a593Smuzhiyun .regmap = NULL, \
78*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
79*4882a593Smuzhiyun &owl_pll_ops, \
80*4882a593Smuzhiyun _flags), \
81*4882a593Smuzhiyun }, \
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
85*4882a593Smuzhiyun _shift, _width, _min_mul, _max_mul, _delay, _table, \
86*4882a593Smuzhiyun _flags) \
87*4882a593Smuzhiyun struct owl_pll _struct = { \
88*4882a593Smuzhiyun .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
89*4882a593Smuzhiyun _width, _min_mul, _max_mul, \
90*4882a593Smuzhiyun _delay, _table), \
91*4882a593Smuzhiyun .common = { \
92*4882a593Smuzhiyun .regmap = NULL, \
93*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
94*4882a593Smuzhiyun &owl_pll_ops, \
95*4882a593Smuzhiyun _flags), \
96*4882a593Smuzhiyun }, \
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define mul_mask(m) ((1 << ((m)->width)) - 1)
100*4882a593Smuzhiyun
hw_to_owl_pll(const struct clk_hw * hw)101*4882a593Smuzhiyun static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct owl_clk_common *common = hw_to_owl_clk_common(hw);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return container_of(common, struct owl_pll, common);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun extern const struct clk_ops owl_pll_ops;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #endif /* _OWL_PLL_H_ */
111