1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // OWL gate clock driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2014 Actions Semi Inc.
6*4882a593Smuzhiyun // Author: David Liu <liuwei@actions-semi.com>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd.
9*4882a593Smuzhiyun // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef _OWL_GATE_H_
12*4882a593Smuzhiyun #define _OWL_GATE_H_
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "owl-common.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct owl_gate_hw {
17*4882a593Smuzhiyun u32 reg;
18*4882a593Smuzhiyun u8 bit_idx;
19*4882a593Smuzhiyun u8 gate_flags;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct owl_gate {
23*4882a593Smuzhiyun struct owl_gate_hw gate_hw;
24*4882a593Smuzhiyun struct owl_clk_common common;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \
28*4882a593Smuzhiyun { \
29*4882a593Smuzhiyun .reg = _reg, \
30*4882a593Smuzhiyun .bit_idx = _bit_idx, \
31*4882a593Smuzhiyun .gate_flags = _gate_flags, \
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define OWL_GATE(_struct, _name, _parent, _reg, \
35*4882a593Smuzhiyun _bit_idx, _gate_flags, _flags) \
36*4882a593Smuzhiyun struct owl_gate _struct = { \
37*4882a593Smuzhiyun .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
38*4882a593Smuzhiyun .common = { \
39*4882a593Smuzhiyun .regmap = NULL, \
40*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
41*4882a593Smuzhiyun _parent, \
42*4882a593Smuzhiyun &owl_gate_ops, \
43*4882a593Smuzhiyun _flags), \
44*4882a593Smuzhiyun } \
45*4882a593Smuzhiyun } \
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \
48*4882a593Smuzhiyun _bit_idx, _gate_flags, _flags) \
49*4882a593Smuzhiyun struct owl_gate _struct = { \
50*4882a593Smuzhiyun .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
51*4882a593Smuzhiyun .common = { \
52*4882a593Smuzhiyun .regmap = NULL, \
53*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
54*4882a593Smuzhiyun &owl_gate_ops, \
55*4882a593Smuzhiyun _flags), \
56*4882a593Smuzhiyun }, \
57*4882a593Smuzhiyun } \
58*4882a593Smuzhiyun
hw_to_owl_gate(const struct clk_hw * hw)59*4882a593Smuzhiyun static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct owl_clk_common *common = hw_to_owl_clk_common(hw);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return container_of(common, struct owl_gate, common);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun void owl_gate_set(const struct owl_clk_common *common,
67*4882a593Smuzhiyun const struct owl_gate_hw *gate_hw, bool enable);
68*4882a593Smuzhiyun int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
69*4882a593Smuzhiyun const struct owl_gate_hw *gate_hw);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun extern const struct clk_ops owl_gate_ops;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #endif /* _OWL_GATE_H_ */
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