1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun // 3*4882a593Smuzhiyun // OWL common clock driver 4*4882a593Smuzhiyun // 5*4882a593Smuzhiyun // Copyright (c) 2014 Actions Semi Inc. 6*4882a593Smuzhiyun // Author: David Liu <liuwei@actions-semi.com> 7*4882a593Smuzhiyun // 8*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd. 9*4882a593Smuzhiyun // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _OWL_COMMON_H_ 12*4882a593Smuzhiyun #define _OWL_COMMON_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/clk-provider.h> 15*4882a593Smuzhiyun #include <linux/of_platform.h> 16*4882a593Smuzhiyun #include <linux/regmap.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct device_node; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct owl_clk_common { 21*4882a593Smuzhiyun struct regmap *regmap; 22*4882a593Smuzhiyun struct clk_hw hw; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct owl_clk_desc { 26*4882a593Smuzhiyun struct owl_clk_common **clks; 27*4882a593Smuzhiyun unsigned long num_clks; 28*4882a593Smuzhiyun struct clk_hw_onecell_data *hw_clks; 29*4882a593Smuzhiyun const struct owl_reset_map *resets; 30*4882a593Smuzhiyun unsigned long num_resets; 31*4882a593Smuzhiyun struct regmap *regmap; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun static inline struct owl_clk_common * hw_to_owl_clk_common(const struct clk_hw * hw)35*4882a593Smuzhiyun hw_to_owl_clk_common(const struct clk_hw *hw) 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun return container_of(hw, struct owl_clk_common, hw); 38*4882a593Smuzhiyun } 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun int owl_clk_regmap_init(struct platform_device *pdev, 41*4882a593Smuzhiyun struct owl_clk_desc *desc); 42*4882a593Smuzhiyun int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* _OWL_COMMON_H_ */ 45