1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/drivers/misc/xillybus.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2011 Xillybus Ltd, http://xillybus.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Header file for the Xillybus FPGA/host framework. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __XILLYBUS_H 11*4882a593Smuzhiyun #define __XILLYBUS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/list.h> 14*4882a593Smuzhiyun #include <linux/device.h> 15*4882a593Smuzhiyun #include <linux/dma-mapping.h> 16*4882a593Smuzhiyun #include <linux/interrupt.h> 17*4882a593Smuzhiyun #include <linux/sched.h> 18*4882a593Smuzhiyun #include <linux/cdev.h> 19*4882a593Smuzhiyun #include <linux/spinlock.h> 20*4882a593Smuzhiyun #include <linux/mutex.h> 21*4882a593Smuzhiyun #include <linux/workqueue.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct xilly_endpoint_hardware; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct xilly_buffer { 26*4882a593Smuzhiyun void *addr; 27*4882a593Smuzhiyun dma_addr_t dma_addr; 28*4882a593Smuzhiyun int end_offset; /* Counting elements, not bytes */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct xilly_idt_handle { 32*4882a593Smuzhiyun unsigned char *chandesc; 33*4882a593Smuzhiyun unsigned char *idt; 34*4882a593Smuzhiyun int entries; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so 39*4882a593Smuzhiyun * wr_* buffers are those consumed by read(), since the FPGA writes to them 40*4882a593Smuzhiyun * and vice versa. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct xilly_channel { 44*4882a593Smuzhiyun struct xilly_endpoint *endpoint; 45*4882a593Smuzhiyun int chan_num; 46*4882a593Smuzhiyun int log2_element_size; 47*4882a593Smuzhiyun int seekable; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */ 50*4882a593Smuzhiyun int num_wr_buffers; 51*4882a593Smuzhiyun unsigned int wr_buf_size; /* In bytes */ 52*4882a593Smuzhiyun int wr_fpga_buf_idx; 53*4882a593Smuzhiyun int wr_host_buf_idx; 54*4882a593Smuzhiyun int wr_host_buf_pos; 55*4882a593Smuzhiyun int wr_empty; 56*4882a593Smuzhiyun int wr_ready; /* Significant only when wr_empty == 1 */ 57*4882a593Smuzhiyun int wr_sleepy; 58*4882a593Smuzhiyun int wr_eof; 59*4882a593Smuzhiyun int wr_hangup; 60*4882a593Smuzhiyun spinlock_t wr_spinlock; 61*4882a593Smuzhiyun struct mutex wr_mutex; 62*4882a593Smuzhiyun wait_queue_head_t wr_wait; 63*4882a593Smuzhiyun wait_queue_head_t wr_ready_wait; 64*4882a593Smuzhiyun int wr_ref_count; 65*4882a593Smuzhiyun int wr_synchronous; 66*4882a593Smuzhiyun int wr_allow_partial; 67*4882a593Smuzhiyun int wr_exclusive_open; 68*4882a593Smuzhiyun int wr_supports_nonempty; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */ 71*4882a593Smuzhiyun int num_rd_buffers; 72*4882a593Smuzhiyun unsigned int rd_buf_size; /* In bytes */ 73*4882a593Smuzhiyun int rd_fpga_buf_idx; 74*4882a593Smuzhiyun int rd_host_buf_pos; 75*4882a593Smuzhiyun int rd_host_buf_idx; 76*4882a593Smuzhiyun int rd_full; 77*4882a593Smuzhiyun spinlock_t rd_spinlock; 78*4882a593Smuzhiyun struct mutex rd_mutex; 79*4882a593Smuzhiyun wait_queue_head_t rd_wait; 80*4882a593Smuzhiyun int rd_ref_count; 81*4882a593Smuzhiyun int rd_allow_partial; 82*4882a593Smuzhiyun int rd_synchronous; 83*4882a593Smuzhiyun int rd_exclusive_open; 84*4882a593Smuzhiyun struct delayed_work rd_workitem; 85*4882a593Smuzhiyun unsigned char rd_leftovers[4]; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct xilly_endpoint { 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * One of pdev and dev is always NULL, and the other is a valid 91*4882a593Smuzhiyun * pointer, depending on the type of device 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun struct pci_dev *pdev; 94*4882a593Smuzhiyun struct device *dev; 95*4882a593Smuzhiyun struct xilly_endpoint_hardware *ephw; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun struct list_head ep_list; 98*4882a593Smuzhiyun int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */ 99*4882a593Smuzhiyun __iomem void *registers; 100*4882a593Smuzhiyun int fatal_error; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun struct mutex register_mutex; 103*4882a593Smuzhiyun wait_queue_head_t ep_wait; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Channels and message handling */ 106*4882a593Smuzhiyun struct cdev cdev; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun int major; 109*4882a593Smuzhiyun int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun int num_channels; /* EXCLUDING message buffer */ 112*4882a593Smuzhiyun struct xilly_channel **channels; 113*4882a593Smuzhiyun int msg_counter; 114*4882a593Smuzhiyun int failed_messages; 115*4882a593Smuzhiyun int idtlen; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun u32 *msgbuf_addr; 118*4882a593Smuzhiyun dma_addr_t msgbuf_dma_addr; 119*4882a593Smuzhiyun unsigned int msg_buf_size; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun struct xilly_endpoint_hardware { 123*4882a593Smuzhiyun struct module *owner; 124*4882a593Smuzhiyun void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *, 125*4882a593Smuzhiyun dma_addr_t, 126*4882a593Smuzhiyun size_t, 127*4882a593Smuzhiyun int); 128*4882a593Smuzhiyun void (*hw_sync_sgl_for_device)(struct xilly_endpoint *, 129*4882a593Smuzhiyun dma_addr_t, 130*4882a593Smuzhiyun size_t, 131*4882a593Smuzhiyun int); 132*4882a593Smuzhiyun int (*map_single)(struct xilly_endpoint *, 133*4882a593Smuzhiyun void *, 134*4882a593Smuzhiyun size_t, 135*4882a593Smuzhiyun int, 136*4882a593Smuzhiyun dma_addr_t *); 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct xilly_mapping { 140*4882a593Smuzhiyun void *device; 141*4882a593Smuzhiyun dma_addr_t dma_addr; 142*4882a593Smuzhiyun size_t size; 143*4882a593Smuzhiyun int direction; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun irqreturn_t xillybus_isr(int irq, void *data); 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev, 149*4882a593Smuzhiyun struct device *dev, 150*4882a593Smuzhiyun struct xilly_endpoint_hardware 151*4882a593Smuzhiyun *ephw); 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint); 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun void xillybus_endpoint_remove(struct xilly_endpoint *endpoint); 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif /* __XILLYBUS_H */ 158