1*4882a593Smuzhiyun /*****************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Author: Xilinx, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the
7*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your
8*4882a593Smuzhiyun * option) any later version.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
11*4882a593Smuzhiyun * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
12*4882a593Smuzhiyun * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
13*4882a593Smuzhiyun * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
14*4882a593Smuzhiyun * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
15*4882a593Smuzhiyun * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
16*4882a593Smuzhiyun * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
17*4882a593Smuzhiyun * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
18*4882a593Smuzhiyun * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
19*4882a593Smuzhiyun * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
20*4882a593Smuzhiyun * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
21*4882a593Smuzhiyun * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22*4882a593Smuzhiyun * FOR A PARTICULAR PURPOSE.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * (c) Copyright 2002 Xilinx Inc., Systems Engineering Group
25*4882a593Smuzhiyun * (c) Copyright 2004 Xilinx Inc., Systems Engineering Group
26*4882a593Smuzhiyun * (c) Copyright 2007-2008 Xilinx Inc.
27*4882a593Smuzhiyun * All rights reserved.
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along
30*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc.,
31*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *****************************************************************************/
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * This is the code behind /dev/icap* -- it allows a user-space
37*4882a593Smuzhiyun * application to use the Xilinx ICAP subsystem.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * The following operations are possible:
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun * open open the port and initialize for access.
42*4882a593Smuzhiyun * release release port
43*4882a593Smuzhiyun * write Write a bitstream to the configuration processor.
44*4882a593Smuzhiyun * read Read a data stream from the configuration processor.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun * After being opened, the port is initialized and accessed to avoid a
47*4882a593Smuzhiyun * corrupted first read which may occur with some hardware. The port
48*4882a593Smuzhiyun * is left in a desynched state, requiring that a synch sequence be
49*4882a593Smuzhiyun * transmitted before any valid configuration data. A user will have
50*4882a593Smuzhiyun * exclusive access to the device while it remains open, and the state
51*4882a593Smuzhiyun * of the ICAP cannot be guaranteed after the device is closed. Note
52*4882a593Smuzhiyun * that a complete reset of the core and the state of the ICAP cannot
53*4882a593Smuzhiyun * be performed on many versions of the cores, hence users of this
54*4882a593Smuzhiyun * device should avoid making inconsistent accesses to the device. In
55*4882a593Smuzhiyun * particular, accessing the read interface, without first generating
56*4882a593Smuzhiyun * a write containing a readback packet can leave the ICAP in an
57*4882a593Smuzhiyun * inaccessible state.
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * Note that in order to use the read interface, it is first necessary
60*4882a593Smuzhiyun * to write a request packet to the write interface. i.e., it is not
61*4882a593Smuzhiyun * possible to simply readback the bitstream (or any configuration
62*4882a593Smuzhiyun * bits) from a device without specifically requesting them first.
63*4882a593Smuzhiyun * The code to craft such packets is intended to be part of the
64*4882a593Smuzhiyun * user-space application code that uses this device. The simplest
65*4882a593Smuzhiyun * way to use this interface is simply:
66*4882a593Smuzhiyun *
67*4882a593Smuzhiyun * cp foo.bit /dev/icap0
68*4882a593Smuzhiyun *
69*4882a593Smuzhiyun * Note that unless foo.bit is an appropriately constructed partial
70*4882a593Smuzhiyun * bitstream, this has a high likelihood of overwriting the design
71*4882a593Smuzhiyun * currently programmed in the FPGA.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #include <linux/module.h>
75*4882a593Smuzhiyun #include <linux/kernel.h>
76*4882a593Smuzhiyun #include <linux/types.h>
77*4882a593Smuzhiyun #include <linux/ioport.h>
78*4882a593Smuzhiyun #include <linux/interrupt.h>
79*4882a593Smuzhiyun #include <linux/fcntl.h>
80*4882a593Smuzhiyun #include <linux/init.h>
81*4882a593Smuzhiyun #include <linux/poll.h>
82*4882a593Smuzhiyun #include <linux/proc_fs.h>
83*4882a593Smuzhiyun #include <linux/mutex.h>
84*4882a593Smuzhiyun #include <linux/sysctl.h>
85*4882a593Smuzhiyun #include <linux/fs.h>
86*4882a593Smuzhiyun #include <linux/cdev.h>
87*4882a593Smuzhiyun #include <linux/platform_device.h>
88*4882a593Smuzhiyun #include <linux/slab.h>
89*4882a593Smuzhiyun #include <linux/io.h>
90*4882a593Smuzhiyun #include <linux/uaccess.h>
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #ifdef CONFIG_OF
93*4882a593Smuzhiyun /* For open firmware. */
94*4882a593Smuzhiyun #include <linux/of_address.h>
95*4882a593Smuzhiyun #include <linux/of_device.h>
96*4882a593Smuzhiyun #include <linux/of_platform.h>
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #include "xilinx_hwicap.h"
100*4882a593Smuzhiyun #include "buffer_icap.h"
101*4882a593Smuzhiyun #include "fifo_icap.h"
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define DRIVER_NAME "icap"
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define HWICAP_REGS (0x10000)
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define XHWICAP_MAJOR 259
108*4882a593Smuzhiyun #define XHWICAP_MINOR 0
109*4882a593Smuzhiyun #define HWICAP_DEVICES 1
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* An array, which is set to true when the device is registered. */
112*4882a593Smuzhiyun static DEFINE_MUTEX(hwicap_mutex);
113*4882a593Smuzhiyun static bool probed_devices[HWICAP_DEVICES];
114*4882a593Smuzhiyun static struct mutex icap_sem;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static struct class *icap_class;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #define UNIMPLEMENTED 0xFFFF
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const struct config_registers v2_config_registers = {
121*4882a593Smuzhiyun .CRC = 0,
122*4882a593Smuzhiyun .FAR = 1,
123*4882a593Smuzhiyun .FDRI = 2,
124*4882a593Smuzhiyun .FDRO = 3,
125*4882a593Smuzhiyun .CMD = 4,
126*4882a593Smuzhiyun .CTL = 5,
127*4882a593Smuzhiyun .MASK = 6,
128*4882a593Smuzhiyun .STAT = 7,
129*4882a593Smuzhiyun .LOUT = 8,
130*4882a593Smuzhiyun .COR = 9,
131*4882a593Smuzhiyun .MFWR = 10,
132*4882a593Smuzhiyun .FLR = 11,
133*4882a593Smuzhiyun .KEY = 12,
134*4882a593Smuzhiyun .CBC = 13,
135*4882a593Smuzhiyun .IDCODE = 14,
136*4882a593Smuzhiyun .AXSS = UNIMPLEMENTED,
137*4882a593Smuzhiyun .C0R_1 = UNIMPLEMENTED,
138*4882a593Smuzhiyun .CSOB = UNIMPLEMENTED,
139*4882a593Smuzhiyun .WBSTAR = UNIMPLEMENTED,
140*4882a593Smuzhiyun .TIMER = UNIMPLEMENTED,
141*4882a593Smuzhiyun .BOOTSTS = UNIMPLEMENTED,
142*4882a593Smuzhiyun .CTL_1 = UNIMPLEMENTED,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct config_registers v4_config_registers = {
146*4882a593Smuzhiyun .CRC = 0,
147*4882a593Smuzhiyun .FAR = 1,
148*4882a593Smuzhiyun .FDRI = 2,
149*4882a593Smuzhiyun .FDRO = 3,
150*4882a593Smuzhiyun .CMD = 4,
151*4882a593Smuzhiyun .CTL = 5,
152*4882a593Smuzhiyun .MASK = 6,
153*4882a593Smuzhiyun .STAT = 7,
154*4882a593Smuzhiyun .LOUT = 8,
155*4882a593Smuzhiyun .COR = 9,
156*4882a593Smuzhiyun .MFWR = 10,
157*4882a593Smuzhiyun .FLR = UNIMPLEMENTED,
158*4882a593Smuzhiyun .KEY = UNIMPLEMENTED,
159*4882a593Smuzhiyun .CBC = 11,
160*4882a593Smuzhiyun .IDCODE = 12,
161*4882a593Smuzhiyun .AXSS = 13,
162*4882a593Smuzhiyun .C0R_1 = UNIMPLEMENTED,
163*4882a593Smuzhiyun .CSOB = UNIMPLEMENTED,
164*4882a593Smuzhiyun .WBSTAR = UNIMPLEMENTED,
165*4882a593Smuzhiyun .TIMER = UNIMPLEMENTED,
166*4882a593Smuzhiyun .BOOTSTS = UNIMPLEMENTED,
167*4882a593Smuzhiyun .CTL_1 = UNIMPLEMENTED,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const struct config_registers v5_config_registers = {
171*4882a593Smuzhiyun .CRC = 0,
172*4882a593Smuzhiyun .FAR = 1,
173*4882a593Smuzhiyun .FDRI = 2,
174*4882a593Smuzhiyun .FDRO = 3,
175*4882a593Smuzhiyun .CMD = 4,
176*4882a593Smuzhiyun .CTL = 5,
177*4882a593Smuzhiyun .MASK = 6,
178*4882a593Smuzhiyun .STAT = 7,
179*4882a593Smuzhiyun .LOUT = 8,
180*4882a593Smuzhiyun .COR = 9,
181*4882a593Smuzhiyun .MFWR = 10,
182*4882a593Smuzhiyun .FLR = UNIMPLEMENTED,
183*4882a593Smuzhiyun .KEY = UNIMPLEMENTED,
184*4882a593Smuzhiyun .CBC = 11,
185*4882a593Smuzhiyun .IDCODE = 12,
186*4882a593Smuzhiyun .AXSS = 13,
187*4882a593Smuzhiyun .C0R_1 = 14,
188*4882a593Smuzhiyun .CSOB = 15,
189*4882a593Smuzhiyun .WBSTAR = 16,
190*4882a593Smuzhiyun .TIMER = 17,
191*4882a593Smuzhiyun .BOOTSTS = 18,
192*4882a593Smuzhiyun .CTL_1 = 19,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const struct config_registers v6_config_registers = {
196*4882a593Smuzhiyun .CRC = 0,
197*4882a593Smuzhiyun .FAR = 1,
198*4882a593Smuzhiyun .FDRI = 2,
199*4882a593Smuzhiyun .FDRO = 3,
200*4882a593Smuzhiyun .CMD = 4,
201*4882a593Smuzhiyun .CTL = 5,
202*4882a593Smuzhiyun .MASK = 6,
203*4882a593Smuzhiyun .STAT = 7,
204*4882a593Smuzhiyun .LOUT = 8,
205*4882a593Smuzhiyun .COR = 9,
206*4882a593Smuzhiyun .MFWR = 10,
207*4882a593Smuzhiyun .FLR = UNIMPLEMENTED,
208*4882a593Smuzhiyun .KEY = UNIMPLEMENTED,
209*4882a593Smuzhiyun .CBC = 11,
210*4882a593Smuzhiyun .IDCODE = 12,
211*4882a593Smuzhiyun .AXSS = 13,
212*4882a593Smuzhiyun .C0R_1 = 14,
213*4882a593Smuzhiyun .CSOB = 15,
214*4882a593Smuzhiyun .WBSTAR = 16,
215*4882a593Smuzhiyun .TIMER = 17,
216*4882a593Smuzhiyun .BOOTSTS = 22,
217*4882a593Smuzhiyun .CTL_1 = 24,
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /**
221*4882a593Smuzhiyun * hwicap_command_desync - Send a DESYNC command to the ICAP port.
222*4882a593Smuzhiyun * @drvdata: a pointer to the drvdata.
223*4882a593Smuzhiyun *
224*4882a593Smuzhiyun * Returns: '0' on success and failure value on error
225*4882a593Smuzhiyun *
226*4882a593Smuzhiyun * This command desynchronizes the ICAP After this command, a
227*4882a593Smuzhiyun * bitstream containing a NULL packet, followed by a SYNCH packet is
228*4882a593Smuzhiyun * required before the ICAP will recognize commands.
229*4882a593Smuzhiyun */
hwicap_command_desync(struct hwicap_drvdata * drvdata)230*4882a593Smuzhiyun static int hwicap_command_desync(struct hwicap_drvdata *drvdata)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun u32 buffer[4];
233*4882a593Smuzhiyun u32 index = 0;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /*
236*4882a593Smuzhiyun * Create the data to be written to the ICAP.
237*4882a593Smuzhiyun */
238*4882a593Smuzhiyun buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1;
239*4882a593Smuzhiyun buffer[index++] = XHI_CMD_DESYNCH;
240*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
241*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /*
244*4882a593Smuzhiyun * Write the data to the FIFO and intiate the transfer of data present
245*4882a593Smuzhiyun * in the FIFO to the ICAP device.
246*4882a593Smuzhiyun */
247*4882a593Smuzhiyun return drvdata->config->set_configuration(drvdata,
248*4882a593Smuzhiyun &buffer[0], index);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /**
252*4882a593Smuzhiyun * hwicap_get_configuration_register - Query a configuration register.
253*4882a593Smuzhiyun * @drvdata: a pointer to the drvdata.
254*4882a593Smuzhiyun * @reg: a constant which represents the configuration
255*4882a593Smuzhiyun * register value to be returned.
256*4882a593Smuzhiyun * Examples: XHI_IDCODE, XHI_FLR.
257*4882a593Smuzhiyun * @reg_data: returns the value of the register.
258*4882a593Smuzhiyun *
259*4882a593Smuzhiyun * Returns: '0' on success and failure value on error
260*4882a593Smuzhiyun *
261*4882a593Smuzhiyun * Sends a query packet to the ICAP and then receives the response.
262*4882a593Smuzhiyun * The icap is left in Synched state.
263*4882a593Smuzhiyun */
hwicap_get_configuration_register(struct hwicap_drvdata * drvdata,u32 reg,u32 * reg_data)264*4882a593Smuzhiyun static int hwicap_get_configuration_register(struct hwicap_drvdata *drvdata,
265*4882a593Smuzhiyun u32 reg, u32 *reg_data)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun int status;
268*4882a593Smuzhiyun u32 buffer[6];
269*4882a593Smuzhiyun u32 index = 0;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun * Create the data to be written to the ICAP.
273*4882a593Smuzhiyun */
274*4882a593Smuzhiyun buffer[index++] = XHI_DUMMY_PACKET;
275*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
276*4882a593Smuzhiyun buffer[index++] = XHI_SYNC_PACKET;
277*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
278*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /*
281*4882a593Smuzhiyun * Write the data to the FIFO and initiate the transfer of data present
282*4882a593Smuzhiyun * in the FIFO to the ICAP device.
283*4882a593Smuzhiyun */
284*4882a593Smuzhiyun status = drvdata->config->set_configuration(drvdata,
285*4882a593Smuzhiyun &buffer[0], index);
286*4882a593Smuzhiyun if (status)
287*4882a593Smuzhiyun return status;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /* If the syncword was not found, then we need to start over. */
290*4882a593Smuzhiyun status = drvdata->config->get_status(drvdata);
291*4882a593Smuzhiyun if ((status & XHI_SR_DALIGN_MASK) != XHI_SR_DALIGN_MASK)
292*4882a593Smuzhiyun return -EIO;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun index = 0;
295*4882a593Smuzhiyun buffer[index++] = hwicap_type_1_read(reg) | 1;
296*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
297*4882a593Smuzhiyun buffer[index++] = XHI_NOOP_PACKET;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun * Write the data to the FIFO and intiate the transfer of data present
301*4882a593Smuzhiyun * in the FIFO to the ICAP device.
302*4882a593Smuzhiyun */
303*4882a593Smuzhiyun status = drvdata->config->set_configuration(drvdata,
304*4882a593Smuzhiyun &buffer[0], index);
305*4882a593Smuzhiyun if (status)
306*4882a593Smuzhiyun return status;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /*
309*4882a593Smuzhiyun * Read the configuration register
310*4882a593Smuzhiyun */
311*4882a593Smuzhiyun status = drvdata->config->get_configuration(drvdata, reg_data, 1);
312*4882a593Smuzhiyun if (status)
313*4882a593Smuzhiyun return status;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return 0;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
hwicap_initialize_hwicap(struct hwicap_drvdata * drvdata)318*4882a593Smuzhiyun static int hwicap_initialize_hwicap(struct hwicap_drvdata *drvdata)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun int status;
321*4882a593Smuzhiyun u32 idcode;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun dev_dbg(drvdata->dev, "initializing\n");
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Abort any current transaction, to make sure we have the
326*4882a593Smuzhiyun * ICAP in a good state.
327*4882a593Smuzhiyun */
328*4882a593Smuzhiyun dev_dbg(drvdata->dev, "Reset...\n");
329*4882a593Smuzhiyun drvdata->config->reset(drvdata);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun dev_dbg(drvdata->dev, "Desync...\n");
332*4882a593Smuzhiyun status = hwicap_command_desync(drvdata);
333*4882a593Smuzhiyun if (status)
334*4882a593Smuzhiyun return status;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* Attempt to read the IDCODE from ICAP. This
337*4882a593Smuzhiyun * may not be returned correctly, due to the design of the
338*4882a593Smuzhiyun * hardware.
339*4882a593Smuzhiyun */
340*4882a593Smuzhiyun dev_dbg(drvdata->dev, "Reading IDCODE...\n");
341*4882a593Smuzhiyun status = hwicap_get_configuration_register(
342*4882a593Smuzhiyun drvdata, drvdata->config_regs->IDCODE, &idcode);
343*4882a593Smuzhiyun dev_dbg(drvdata->dev, "IDCODE = %x\n", idcode);
344*4882a593Smuzhiyun if (status)
345*4882a593Smuzhiyun return status;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun dev_dbg(drvdata->dev, "Desync...\n");
348*4882a593Smuzhiyun status = hwicap_command_desync(drvdata);
349*4882a593Smuzhiyun if (status)
350*4882a593Smuzhiyun return status;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun static ssize_t
hwicap_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)356*4882a593Smuzhiyun hwicap_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun struct hwicap_drvdata *drvdata = file->private_data;
359*4882a593Smuzhiyun ssize_t bytes_to_read = 0;
360*4882a593Smuzhiyun u32 *kbuf;
361*4882a593Smuzhiyun u32 words;
362*4882a593Smuzhiyun u32 bytes_remaining;
363*4882a593Smuzhiyun int status;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun status = mutex_lock_interruptible(&drvdata->sem);
366*4882a593Smuzhiyun if (status)
367*4882a593Smuzhiyun return status;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun if (drvdata->read_buffer_in_use) {
370*4882a593Smuzhiyun /* If there are leftover bytes in the buffer, just */
371*4882a593Smuzhiyun /* return them and don't try to read more from the */
372*4882a593Smuzhiyun /* ICAP device. */
373*4882a593Smuzhiyun bytes_to_read =
374*4882a593Smuzhiyun (count < drvdata->read_buffer_in_use) ? count :
375*4882a593Smuzhiyun drvdata->read_buffer_in_use;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* Return the data currently in the read buffer. */
378*4882a593Smuzhiyun if (copy_to_user(buf, drvdata->read_buffer, bytes_to_read)) {
379*4882a593Smuzhiyun status = -EFAULT;
380*4882a593Smuzhiyun goto error;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun drvdata->read_buffer_in_use -= bytes_to_read;
383*4882a593Smuzhiyun memmove(drvdata->read_buffer,
384*4882a593Smuzhiyun drvdata->read_buffer + bytes_to_read,
385*4882a593Smuzhiyun 4 - bytes_to_read);
386*4882a593Smuzhiyun } else {
387*4882a593Smuzhiyun /* Get new data from the ICAP, and return was was requested. */
388*4882a593Smuzhiyun kbuf = (u32 *) get_zeroed_page(GFP_KERNEL);
389*4882a593Smuzhiyun if (!kbuf) {
390*4882a593Smuzhiyun status = -ENOMEM;
391*4882a593Smuzhiyun goto error;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /* The ICAP device is only able to read complete */
395*4882a593Smuzhiyun /* words. If a number of bytes that do not correspond */
396*4882a593Smuzhiyun /* to complete words is requested, then we read enough */
397*4882a593Smuzhiyun /* words to get the required number of bytes, and then */
398*4882a593Smuzhiyun /* save the remaining bytes for the next read. */
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun /* Determine the number of words to read, rounding up */
401*4882a593Smuzhiyun /* if necessary. */
402*4882a593Smuzhiyun words = ((count + 3) >> 2);
403*4882a593Smuzhiyun bytes_to_read = words << 2;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun if (bytes_to_read > PAGE_SIZE)
406*4882a593Smuzhiyun bytes_to_read = PAGE_SIZE;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /* Ensure we only read a complete number of words. */
409*4882a593Smuzhiyun bytes_remaining = bytes_to_read & 3;
410*4882a593Smuzhiyun bytes_to_read &= ~3;
411*4882a593Smuzhiyun words = bytes_to_read >> 2;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun status = drvdata->config->get_configuration(drvdata,
414*4882a593Smuzhiyun kbuf, words);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun /* If we didn't read correctly, then bail out. */
417*4882a593Smuzhiyun if (status) {
418*4882a593Smuzhiyun free_page((unsigned long)kbuf);
419*4882a593Smuzhiyun goto error;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /* If we fail to return the data to the user, then bail out. */
423*4882a593Smuzhiyun if (copy_to_user(buf, kbuf, bytes_to_read)) {
424*4882a593Smuzhiyun free_page((unsigned long)kbuf);
425*4882a593Smuzhiyun status = -EFAULT;
426*4882a593Smuzhiyun goto error;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun memcpy(drvdata->read_buffer,
429*4882a593Smuzhiyun kbuf,
430*4882a593Smuzhiyun bytes_remaining);
431*4882a593Smuzhiyun drvdata->read_buffer_in_use = bytes_remaining;
432*4882a593Smuzhiyun free_page((unsigned long)kbuf);
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun status = bytes_to_read;
435*4882a593Smuzhiyun error:
436*4882a593Smuzhiyun mutex_unlock(&drvdata->sem);
437*4882a593Smuzhiyun return status;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun static ssize_t
hwicap_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)441*4882a593Smuzhiyun hwicap_write(struct file *file, const char __user *buf,
442*4882a593Smuzhiyun size_t count, loff_t *ppos)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun struct hwicap_drvdata *drvdata = file->private_data;
445*4882a593Smuzhiyun ssize_t written = 0;
446*4882a593Smuzhiyun ssize_t left = count;
447*4882a593Smuzhiyun u32 *kbuf;
448*4882a593Smuzhiyun ssize_t len;
449*4882a593Smuzhiyun ssize_t status;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun status = mutex_lock_interruptible(&drvdata->sem);
452*4882a593Smuzhiyun if (status)
453*4882a593Smuzhiyun return status;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun left += drvdata->write_buffer_in_use;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /* Only write multiples of 4 bytes. */
458*4882a593Smuzhiyun if (left < 4) {
459*4882a593Smuzhiyun status = 0;
460*4882a593Smuzhiyun goto error;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun kbuf = (u32 *) __get_free_page(GFP_KERNEL);
464*4882a593Smuzhiyun if (!kbuf) {
465*4882a593Smuzhiyun status = -ENOMEM;
466*4882a593Smuzhiyun goto error;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun while (left > 3) {
470*4882a593Smuzhiyun /* only write multiples of 4 bytes, so there might */
471*4882a593Smuzhiyun /* be as many as 3 bytes left (at the end). */
472*4882a593Smuzhiyun len = left;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (len > PAGE_SIZE)
475*4882a593Smuzhiyun len = PAGE_SIZE;
476*4882a593Smuzhiyun len &= ~3;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun if (drvdata->write_buffer_in_use) {
479*4882a593Smuzhiyun memcpy(kbuf, drvdata->write_buffer,
480*4882a593Smuzhiyun drvdata->write_buffer_in_use);
481*4882a593Smuzhiyun if (copy_from_user(
482*4882a593Smuzhiyun (((char *)kbuf) + drvdata->write_buffer_in_use),
483*4882a593Smuzhiyun buf + written,
484*4882a593Smuzhiyun len - (drvdata->write_buffer_in_use))) {
485*4882a593Smuzhiyun free_page((unsigned long)kbuf);
486*4882a593Smuzhiyun status = -EFAULT;
487*4882a593Smuzhiyun goto error;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun } else {
490*4882a593Smuzhiyun if (copy_from_user(kbuf, buf + written, len)) {
491*4882a593Smuzhiyun free_page((unsigned long)kbuf);
492*4882a593Smuzhiyun status = -EFAULT;
493*4882a593Smuzhiyun goto error;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun status = drvdata->config->set_configuration(drvdata,
498*4882a593Smuzhiyun kbuf, len >> 2);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun if (status) {
501*4882a593Smuzhiyun free_page((unsigned long)kbuf);
502*4882a593Smuzhiyun status = -EFAULT;
503*4882a593Smuzhiyun goto error;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun if (drvdata->write_buffer_in_use) {
506*4882a593Smuzhiyun len -= drvdata->write_buffer_in_use;
507*4882a593Smuzhiyun left -= drvdata->write_buffer_in_use;
508*4882a593Smuzhiyun drvdata->write_buffer_in_use = 0;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun written += len;
511*4882a593Smuzhiyun left -= len;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun if ((left > 0) && (left < 4)) {
514*4882a593Smuzhiyun if (!copy_from_user(drvdata->write_buffer,
515*4882a593Smuzhiyun buf + written, left)) {
516*4882a593Smuzhiyun drvdata->write_buffer_in_use = left;
517*4882a593Smuzhiyun written += left;
518*4882a593Smuzhiyun left = 0;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun free_page((unsigned long)kbuf);
523*4882a593Smuzhiyun status = written;
524*4882a593Smuzhiyun error:
525*4882a593Smuzhiyun mutex_unlock(&drvdata->sem);
526*4882a593Smuzhiyun return status;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
hwicap_open(struct inode * inode,struct file * file)529*4882a593Smuzhiyun static int hwicap_open(struct inode *inode, struct file *file)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun struct hwicap_drvdata *drvdata;
532*4882a593Smuzhiyun int status;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun mutex_lock(&hwicap_mutex);
535*4882a593Smuzhiyun drvdata = container_of(inode->i_cdev, struct hwicap_drvdata, cdev);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun status = mutex_lock_interruptible(&drvdata->sem);
538*4882a593Smuzhiyun if (status)
539*4882a593Smuzhiyun goto out;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if (drvdata->is_open) {
542*4882a593Smuzhiyun status = -EBUSY;
543*4882a593Smuzhiyun goto error;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun status = hwicap_initialize_hwicap(drvdata);
547*4882a593Smuzhiyun if (status) {
548*4882a593Smuzhiyun dev_err(drvdata->dev, "Failed to open file");
549*4882a593Smuzhiyun goto error;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun file->private_data = drvdata;
553*4882a593Smuzhiyun drvdata->write_buffer_in_use = 0;
554*4882a593Smuzhiyun drvdata->read_buffer_in_use = 0;
555*4882a593Smuzhiyun drvdata->is_open = 1;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun error:
558*4882a593Smuzhiyun mutex_unlock(&drvdata->sem);
559*4882a593Smuzhiyun out:
560*4882a593Smuzhiyun mutex_unlock(&hwicap_mutex);
561*4882a593Smuzhiyun return status;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun
hwicap_release(struct inode * inode,struct file * file)564*4882a593Smuzhiyun static int hwicap_release(struct inode *inode, struct file *file)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun struct hwicap_drvdata *drvdata = file->private_data;
567*4882a593Smuzhiyun int i;
568*4882a593Smuzhiyun int status = 0;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun mutex_lock(&drvdata->sem);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun if (drvdata->write_buffer_in_use) {
573*4882a593Smuzhiyun /* Flush write buffer. */
574*4882a593Smuzhiyun for (i = drvdata->write_buffer_in_use; i < 4; i++)
575*4882a593Smuzhiyun drvdata->write_buffer[i] = 0;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun status = drvdata->config->set_configuration(drvdata,
578*4882a593Smuzhiyun (u32 *) drvdata->write_buffer, 1);
579*4882a593Smuzhiyun if (status)
580*4882a593Smuzhiyun goto error;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun status = hwicap_command_desync(drvdata);
584*4882a593Smuzhiyun if (status)
585*4882a593Smuzhiyun goto error;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun error:
588*4882a593Smuzhiyun drvdata->is_open = 0;
589*4882a593Smuzhiyun mutex_unlock(&drvdata->sem);
590*4882a593Smuzhiyun return status;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun static const struct file_operations hwicap_fops = {
594*4882a593Smuzhiyun .owner = THIS_MODULE,
595*4882a593Smuzhiyun .write = hwicap_write,
596*4882a593Smuzhiyun .read = hwicap_read,
597*4882a593Smuzhiyun .open = hwicap_open,
598*4882a593Smuzhiyun .release = hwicap_release,
599*4882a593Smuzhiyun .llseek = noop_llseek,
600*4882a593Smuzhiyun };
601*4882a593Smuzhiyun
hwicap_setup(struct device * dev,int id,const struct resource * regs_res,const struct hwicap_driver_config * config,const struct config_registers * config_regs)602*4882a593Smuzhiyun static int hwicap_setup(struct device *dev, int id,
603*4882a593Smuzhiyun const struct resource *regs_res,
604*4882a593Smuzhiyun const struct hwicap_driver_config *config,
605*4882a593Smuzhiyun const struct config_registers *config_regs)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun dev_t devt;
608*4882a593Smuzhiyun struct hwicap_drvdata *drvdata = NULL;
609*4882a593Smuzhiyun int retval = 0;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun dev_info(dev, "Xilinx icap port driver\n");
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun mutex_lock(&icap_sem);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun if (id < 0) {
616*4882a593Smuzhiyun for (id = 0; id < HWICAP_DEVICES; id++)
617*4882a593Smuzhiyun if (!probed_devices[id])
618*4882a593Smuzhiyun break;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun if (id < 0 || id >= HWICAP_DEVICES) {
621*4882a593Smuzhiyun mutex_unlock(&icap_sem);
622*4882a593Smuzhiyun dev_err(dev, "%s%i too large\n", DRIVER_NAME, id);
623*4882a593Smuzhiyun return -EINVAL;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun if (probed_devices[id]) {
626*4882a593Smuzhiyun mutex_unlock(&icap_sem);
627*4882a593Smuzhiyun dev_err(dev, "cannot assign to %s%i; it is already in use\n",
628*4882a593Smuzhiyun DRIVER_NAME, id);
629*4882a593Smuzhiyun return -EBUSY;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun probed_devices[id] = 1;
633*4882a593Smuzhiyun mutex_unlock(&icap_sem);
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR + id);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun drvdata = kzalloc(sizeof(struct hwicap_drvdata), GFP_KERNEL);
638*4882a593Smuzhiyun if (!drvdata) {
639*4882a593Smuzhiyun retval = -ENOMEM;
640*4882a593Smuzhiyun goto failed0;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun dev_set_drvdata(dev, (void *)drvdata);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun if (!regs_res) {
645*4882a593Smuzhiyun dev_err(dev, "Couldn't get registers resource\n");
646*4882a593Smuzhiyun retval = -EFAULT;
647*4882a593Smuzhiyun goto failed1;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun drvdata->mem_start = regs_res->start;
651*4882a593Smuzhiyun drvdata->mem_end = regs_res->end;
652*4882a593Smuzhiyun drvdata->mem_size = resource_size(regs_res);
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun if (!request_mem_region(drvdata->mem_start,
655*4882a593Smuzhiyun drvdata->mem_size, DRIVER_NAME)) {
656*4882a593Smuzhiyun dev_err(dev, "Couldn't lock memory region at %Lx\n",
657*4882a593Smuzhiyun (unsigned long long) regs_res->start);
658*4882a593Smuzhiyun retval = -EBUSY;
659*4882a593Smuzhiyun goto failed1;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun drvdata->devt = devt;
663*4882a593Smuzhiyun drvdata->dev = dev;
664*4882a593Smuzhiyun drvdata->base_address = ioremap(drvdata->mem_start, drvdata->mem_size);
665*4882a593Smuzhiyun if (!drvdata->base_address) {
666*4882a593Smuzhiyun dev_err(dev, "ioremap() failed\n");
667*4882a593Smuzhiyun retval = -ENOMEM;
668*4882a593Smuzhiyun goto failed2;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun drvdata->config = config;
672*4882a593Smuzhiyun drvdata->config_regs = config_regs;
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun mutex_init(&drvdata->sem);
675*4882a593Smuzhiyun drvdata->is_open = 0;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun dev_info(dev, "ioremap %llx to %p with size %llx\n",
678*4882a593Smuzhiyun (unsigned long long) drvdata->mem_start,
679*4882a593Smuzhiyun drvdata->base_address,
680*4882a593Smuzhiyun (unsigned long long) drvdata->mem_size);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun cdev_init(&drvdata->cdev, &hwicap_fops);
683*4882a593Smuzhiyun drvdata->cdev.owner = THIS_MODULE;
684*4882a593Smuzhiyun retval = cdev_add(&drvdata->cdev, devt, 1);
685*4882a593Smuzhiyun if (retval) {
686*4882a593Smuzhiyun dev_err(dev, "cdev_add() failed\n");
687*4882a593Smuzhiyun goto failed3;
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun device_create(icap_class, dev, devt, NULL, "%s%d", DRIVER_NAME, id);
691*4882a593Smuzhiyun return 0; /* success */
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun failed3:
694*4882a593Smuzhiyun iounmap(drvdata->base_address);
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun failed2:
697*4882a593Smuzhiyun release_mem_region(regs_res->start, drvdata->mem_size);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun failed1:
700*4882a593Smuzhiyun kfree(drvdata);
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun failed0:
703*4882a593Smuzhiyun mutex_lock(&icap_sem);
704*4882a593Smuzhiyun probed_devices[id] = 0;
705*4882a593Smuzhiyun mutex_unlock(&icap_sem);
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun return retval;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun static struct hwicap_driver_config buffer_icap_config = {
711*4882a593Smuzhiyun .get_configuration = buffer_icap_get_configuration,
712*4882a593Smuzhiyun .set_configuration = buffer_icap_set_configuration,
713*4882a593Smuzhiyun .get_status = buffer_icap_get_status,
714*4882a593Smuzhiyun .reset = buffer_icap_reset,
715*4882a593Smuzhiyun };
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun static struct hwicap_driver_config fifo_icap_config = {
718*4882a593Smuzhiyun .get_configuration = fifo_icap_get_configuration,
719*4882a593Smuzhiyun .set_configuration = fifo_icap_set_configuration,
720*4882a593Smuzhiyun .get_status = fifo_icap_get_status,
721*4882a593Smuzhiyun .reset = fifo_icap_reset,
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun
hwicap_remove(struct device * dev)724*4882a593Smuzhiyun static int hwicap_remove(struct device *dev)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun struct hwicap_drvdata *drvdata;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun drvdata = dev_get_drvdata(dev);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (!drvdata)
731*4882a593Smuzhiyun return 0;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun device_destroy(icap_class, drvdata->devt);
734*4882a593Smuzhiyun cdev_del(&drvdata->cdev);
735*4882a593Smuzhiyun iounmap(drvdata->base_address);
736*4882a593Smuzhiyun release_mem_region(drvdata->mem_start, drvdata->mem_size);
737*4882a593Smuzhiyun kfree(drvdata);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun mutex_lock(&icap_sem);
740*4882a593Smuzhiyun probed_devices[MINOR(dev->devt)-XHWICAP_MINOR] = 0;
741*4882a593Smuzhiyun mutex_unlock(&icap_sem);
742*4882a593Smuzhiyun return 0; /* success */
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun #ifdef CONFIG_OF
hwicap_of_probe(struct platform_device * op,const struct hwicap_driver_config * config)746*4882a593Smuzhiyun static int hwicap_of_probe(struct platform_device *op,
747*4882a593Smuzhiyun const struct hwicap_driver_config *config)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun struct resource res;
750*4882a593Smuzhiyun const unsigned int *id;
751*4882a593Smuzhiyun const char *family;
752*4882a593Smuzhiyun int rc;
753*4882a593Smuzhiyun const struct config_registers *regs;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun rc = of_address_to_resource(op->dev.of_node, 0, &res);
757*4882a593Smuzhiyun if (rc) {
758*4882a593Smuzhiyun dev_err(&op->dev, "invalid address\n");
759*4882a593Smuzhiyun return rc;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun id = of_get_property(op->dev.of_node, "port-number", NULL);
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun /* It's most likely that we're using V4, if the family is not
765*4882a593Smuzhiyun * specified
766*4882a593Smuzhiyun */
767*4882a593Smuzhiyun regs = &v4_config_registers;
768*4882a593Smuzhiyun family = of_get_property(op->dev.of_node, "xlnx,family", NULL);
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun if (family) {
771*4882a593Smuzhiyun if (!strcmp(family, "virtex2p"))
772*4882a593Smuzhiyun regs = &v2_config_registers;
773*4882a593Smuzhiyun else if (!strcmp(family, "virtex4"))
774*4882a593Smuzhiyun regs = &v4_config_registers;
775*4882a593Smuzhiyun else if (!strcmp(family, "virtex5"))
776*4882a593Smuzhiyun regs = &v5_config_registers;
777*4882a593Smuzhiyun else if (!strcmp(family, "virtex6"))
778*4882a593Smuzhiyun regs = &v6_config_registers;
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun return hwicap_setup(&op->dev, id ? *id : -1, &res, config,
781*4882a593Smuzhiyun regs);
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun #else
hwicap_of_probe(struct platform_device * op,const struct hwicap_driver_config * config)784*4882a593Smuzhiyun static inline int hwicap_of_probe(struct platform_device *op,
785*4882a593Smuzhiyun const struct hwicap_driver_config *config)
786*4882a593Smuzhiyun {
787*4882a593Smuzhiyun return -EINVAL;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun #endif /* CONFIG_OF */
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun static const struct of_device_id hwicap_of_match[];
hwicap_drv_probe(struct platform_device * pdev)792*4882a593Smuzhiyun static int hwicap_drv_probe(struct platform_device *pdev)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun const struct of_device_id *match;
795*4882a593Smuzhiyun struct resource *res;
796*4882a593Smuzhiyun const struct config_registers *regs;
797*4882a593Smuzhiyun const char *family;
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun match = of_match_device(hwicap_of_match, &pdev->dev);
800*4882a593Smuzhiyun if (match)
801*4882a593Smuzhiyun return hwicap_of_probe(pdev, match->data);
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804*4882a593Smuzhiyun if (!res)
805*4882a593Smuzhiyun return -ENODEV;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun /* It's most likely that we're using V4, if the family is not
808*4882a593Smuzhiyun * specified
809*4882a593Smuzhiyun */
810*4882a593Smuzhiyun regs = &v4_config_registers;
811*4882a593Smuzhiyun family = pdev->dev.platform_data;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun if (family) {
814*4882a593Smuzhiyun if (!strcmp(family, "virtex2p"))
815*4882a593Smuzhiyun regs = &v2_config_registers;
816*4882a593Smuzhiyun else if (!strcmp(family, "virtex4"))
817*4882a593Smuzhiyun regs = &v4_config_registers;
818*4882a593Smuzhiyun else if (!strcmp(family, "virtex5"))
819*4882a593Smuzhiyun regs = &v5_config_registers;
820*4882a593Smuzhiyun else if (!strcmp(family, "virtex6"))
821*4882a593Smuzhiyun regs = &v6_config_registers;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun return hwicap_setup(&pdev->dev, pdev->id, res,
825*4882a593Smuzhiyun &buffer_icap_config, regs);
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
hwicap_drv_remove(struct platform_device * pdev)828*4882a593Smuzhiyun static int hwicap_drv_remove(struct platform_device *pdev)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun return hwicap_remove(&pdev->dev);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun #ifdef CONFIG_OF
834*4882a593Smuzhiyun /* Match table for device tree binding */
835*4882a593Smuzhiyun static const struct of_device_id hwicap_of_match[] = {
836*4882a593Smuzhiyun { .compatible = "xlnx,opb-hwicap-1.00.b", .data = &buffer_icap_config},
837*4882a593Smuzhiyun { .compatible = "xlnx,xps-hwicap-1.00.a", .data = &fifo_icap_config},
838*4882a593Smuzhiyun {},
839*4882a593Smuzhiyun };
840*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hwicap_of_match);
841*4882a593Smuzhiyun #else
842*4882a593Smuzhiyun #define hwicap_of_match NULL
843*4882a593Smuzhiyun #endif
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun static struct platform_driver hwicap_platform_driver = {
846*4882a593Smuzhiyun .probe = hwicap_drv_probe,
847*4882a593Smuzhiyun .remove = hwicap_drv_remove,
848*4882a593Smuzhiyun .driver = {
849*4882a593Smuzhiyun .name = DRIVER_NAME,
850*4882a593Smuzhiyun .of_match_table = hwicap_of_match,
851*4882a593Smuzhiyun },
852*4882a593Smuzhiyun };
853*4882a593Smuzhiyun
hwicap_module_init(void)854*4882a593Smuzhiyun static int __init hwicap_module_init(void)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun dev_t devt;
857*4882a593Smuzhiyun int retval;
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun icap_class = class_create(THIS_MODULE, "xilinx_config");
860*4882a593Smuzhiyun mutex_init(&icap_sem);
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
863*4882a593Smuzhiyun retval = register_chrdev_region(devt,
864*4882a593Smuzhiyun HWICAP_DEVICES,
865*4882a593Smuzhiyun DRIVER_NAME);
866*4882a593Smuzhiyun if (retval < 0)
867*4882a593Smuzhiyun return retval;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun retval = platform_driver_register(&hwicap_platform_driver);
870*4882a593Smuzhiyun if (retval)
871*4882a593Smuzhiyun goto failed;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun return retval;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun failed:
876*4882a593Smuzhiyun unregister_chrdev_region(devt, HWICAP_DEVICES);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun return retval;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
hwicap_module_cleanup(void)881*4882a593Smuzhiyun static void __exit hwicap_module_cleanup(void)
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun dev_t devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun class_destroy(icap_class);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun platform_driver_unregister(&hwicap_platform_driver);
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun unregister_chrdev_region(devt, HWICAP_DEVICES);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun module_init(hwicap_module_init);
893*4882a593Smuzhiyun module_exit(hwicap_module_cleanup);
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun MODULE_AUTHOR("Xilinx, Inc; Xilinx Research Labs Group");
896*4882a593Smuzhiyun MODULE_DESCRIPTION("Xilinx ICAP Port Driver");
897*4882a593Smuzhiyun MODULE_LICENSE("GPL");
898