1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /******************************************************************************
3*4882a593Smuzhiyun * Nuvoton TPM I2C Device Driver Interface for WPCT301/NPCT501/NPCT6XX,
4*4882a593Smuzhiyun * based on the TCG TPM Interface Spec version 1.2.
5*4882a593Smuzhiyun * Specifications at www.trustedcomputinggroup.org
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2011, Nuvoton Technology Corporation.
8*4882a593Smuzhiyun * Dan Morav <dan.morav@nuvoton.com>
9*4882a593Smuzhiyun * Copyright (C) 2013, Obsidian Research Corp.
10*4882a593Smuzhiyun * Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Nuvoton contact information: APC.Support@nuvoton.com
13*4882a593Smuzhiyun *****************************************************************************/
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/moduleparam.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/wait.h>
21*4882a593Smuzhiyun #include <linux/i2c.h>
22*4882a593Smuzhiyun #include <linux/of_device.h>
23*4882a593Smuzhiyun #include "tpm.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* I2C interface offsets */
26*4882a593Smuzhiyun #define TPM_STS 0x00
27*4882a593Smuzhiyun #define TPM_BURST_COUNT 0x01
28*4882a593Smuzhiyun #define TPM_DATA_FIFO_W 0x20
29*4882a593Smuzhiyun #define TPM_DATA_FIFO_R 0x40
30*4882a593Smuzhiyun #define TPM_VID_DID_RID 0x60
31*4882a593Smuzhiyun #define TPM_I2C_RETRIES 5
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * I2C bus device maximum buffer size w/o counting I2C address or command
34*4882a593Smuzhiyun * i.e. max size required for I2C write is 34 = addr, command, 32 bytes data
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define TPM_I2C_MAX_BUF_SIZE 32
37*4882a593Smuzhiyun #define TPM_I2C_RETRY_COUNT 32
38*4882a593Smuzhiyun #define TPM_I2C_BUS_DELAY 1000 /* usec */
39*4882a593Smuzhiyun #define TPM_I2C_RETRY_DELAY_SHORT (2 * 1000) /* usec */
40*4882a593Smuzhiyun #define TPM_I2C_RETRY_DELAY_LONG (10 * 1000) /* usec */
41*4882a593Smuzhiyun #define TPM_I2C_DELAY_RANGE 300 /* usec */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define OF_IS_TPM2 ((void *)1)
44*4882a593Smuzhiyun #define I2C_IS_TPM2 1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct priv_data {
47*4882a593Smuzhiyun int irq;
48*4882a593Smuzhiyun unsigned int intrs;
49*4882a593Smuzhiyun wait_queue_head_t read_queue;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
i2c_nuvoton_read_buf(struct i2c_client * client,u8 offset,u8 size,u8 * data)52*4882a593Smuzhiyun static s32 i2c_nuvoton_read_buf(struct i2c_client *client, u8 offset, u8 size,
53*4882a593Smuzhiyun u8 *data)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun s32 status;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun status = i2c_smbus_read_i2c_block_data(client, offset, size, data);
58*4882a593Smuzhiyun dev_dbg(&client->dev,
59*4882a593Smuzhiyun "%s(offset=%u size=%u data=%*ph) -> sts=%d\n", __func__,
60*4882a593Smuzhiyun offset, size, (int)size, data, status);
61*4882a593Smuzhiyun return status;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
i2c_nuvoton_write_buf(struct i2c_client * client,u8 offset,u8 size,u8 * data)64*4882a593Smuzhiyun static s32 i2c_nuvoton_write_buf(struct i2c_client *client, u8 offset, u8 size,
65*4882a593Smuzhiyun u8 *data)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun s32 status;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun status = i2c_smbus_write_i2c_block_data(client, offset, size, data);
70*4882a593Smuzhiyun dev_dbg(&client->dev,
71*4882a593Smuzhiyun "%s(offset=%u size=%u data=%*ph) -> sts=%d\n", __func__,
72*4882a593Smuzhiyun offset, size, (int)size, data, status);
73*4882a593Smuzhiyun return status;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define TPM_STS_VALID 0x80
77*4882a593Smuzhiyun #define TPM_STS_COMMAND_READY 0x40
78*4882a593Smuzhiyun #define TPM_STS_GO 0x20
79*4882a593Smuzhiyun #define TPM_STS_DATA_AVAIL 0x10
80*4882a593Smuzhiyun #define TPM_STS_EXPECT 0x08
81*4882a593Smuzhiyun #define TPM_STS_RESPONSE_RETRY 0x02
82*4882a593Smuzhiyun #define TPM_STS_ERR_VAL 0x07 /* bit2...bit0 reads always 0 */
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define TPM_I2C_SHORT_TIMEOUT 750 /* ms */
85*4882a593Smuzhiyun #define TPM_I2C_LONG_TIMEOUT 2000 /* 2 sec */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* read TPM_STS register */
i2c_nuvoton_read_status(struct tpm_chip * chip)88*4882a593Smuzhiyun static u8 i2c_nuvoton_read_status(struct tpm_chip *chip)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(chip->dev.parent);
91*4882a593Smuzhiyun s32 status;
92*4882a593Smuzhiyun u8 data;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun status = i2c_nuvoton_read_buf(client, TPM_STS, 1, &data);
95*4882a593Smuzhiyun if (status <= 0) {
96*4882a593Smuzhiyun dev_err(&chip->dev, "%s() error return %d\n", __func__,
97*4882a593Smuzhiyun status);
98*4882a593Smuzhiyun data = TPM_STS_ERR_VAL;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return data;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* write byte to TPM_STS register */
i2c_nuvoton_write_status(struct i2c_client * client,u8 data)105*4882a593Smuzhiyun static s32 i2c_nuvoton_write_status(struct i2c_client *client, u8 data)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun s32 status;
108*4882a593Smuzhiyun int i;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* this causes the current command to be aborted */
111*4882a593Smuzhiyun for (i = 0, status = -1; i < TPM_I2C_RETRY_COUNT && status < 0; i++) {
112*4882a593Smuzhiyun status = i2c_nuvoton_write_buf(client, TPM_STS, 1, &data);
113*4882a593Smuzhiyun if (status < 0)
114*4882a593Smuzhiyun usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY
115*4882a593Smuzhiyun + TPM_I2C_DELAY_RANGE);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun return status;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* write commandReady to TPM_STS register */
i2c_nuvoton_ready(struct tpm_chip * chip)121*4882a593Smuzhiyun static void i2c_nuvoton_ready(struct tpm_chip *chip)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(chip->dev.parent);
124*4882a593Smuzhiyun s32 status;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* this causes the current command to be aborted */
127*4882a593Smuzhiyun status = i2c_nuvoton_write_status(client, TPM_STS_COMMAND_READY);
128*4882a593Smuzhiyun if (status < 0)
129*4882a593Smuzhiyun dev_err(&chip->dev,
130*4882a593Smuzhiyun "%s() fail to write TPM_STS.commandReady\n", __func__);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* read burstCount field from TPM_STS register
134*4882a593Smuzhiyun * return -1 on fail to read */
i2c_nuvoton_get_burstcount(struct i2c_client * client,struct tpm_chip * chip)135*4882a593Smuzhiyun static int i2c_nuvoton_get_burstcount(struct i2c_client *client,
136*4882a593Smuzhiyun struct tpm_chip *chip)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun unsigned long stop = jiffies + chip->timeout_d;
139*4882a593Smuzhiyun s32 status;
140*4882a593Smuzhiyun int burst_count = -1;
141*4882a593Smuzhiyun u8 data;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* wait for burstcount to be non-zero */
144*4882a593Smuzhiyun do {
145*4882a593Smuzhiyun /* in I2C burstCount is 1 byte */
146*4882a593Smuzhiyun status = i2c_nuvoton_read_buf(client, TPM_BURST_COUNT, 1,
147*4882a593Smuzhiyun &data);
148*4882a593Smuzhiyun if (status > 0 && data > 0) {
149*4882a593Smuzhiyun burst_count = min_t(u8, TPM_I2C_MAX_BUF_SIZE, data);
150*4882a593Smuzhiyun break;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY
153*4882a593Smuzhiyun + TPM_I2C_DELAY_RANGE);
154*4882a593Smuzhiyun } while (time_before(jiffies, stop));
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return burst_count;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun * WPCT301/NPCT501/NPCT6XX SINT# supports only dataAvail
161*4882a593Smuzhiyun * any call to this function which is not waiting for dataAvail will
162*4882a593Smuzhiyun * set queue to NULL to avoid waiting for interrupt
163*4882a593Smuzhiyun */
i2c_nuvoton_check_status(struct tpm_chip * chip,u8 mask,u8 value)164*4882a593Smuzhiyun static bool i2c_nuvoton_check_status(struct tpm_chip *chip, u8 mask, u8 value)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun u8 status = i2c_nuvoton_read_status(chip);
167*4882a593Smuzhiyun return (status != TPM_STS_ERR_VAL) && ((status & mask) == value);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
i2c_nuvoton_wait_for_stat(struct tpm_chip * chip,u8 mask,u8 value,u32 timeout,wait_queue_head_t * queue)170*4882a593Smuzhiyun static int i2c_nuvoton_wait_for_stat(struct tpm_chip *chip, u8 mask, u8 value,
171*4882a593Smuzhiyun u32 timeout, wait_queue_head_t *queue)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun if ((chip->flags & TPM_CHIP_FLAG_IRQ) && queue) {
174*4882a593Smuzhiyun s32 rc;
175*4882a593Smuzhiyun struct priv_data *priv = dev_get_drvdata(&chip->dev);
176*4882a593Smuzhiyun unsigned int cur_intrs = priv->intrs;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun enable_irq(priv->irq);
179*4882a593Smuzhiyun rc = wait_event_interruptible_timeout(*queue,
180*4882a593Smuzhiyun cur_intrs != priv->intrs,
181*4882a593Smuzhiyun timeout);
182*4882a593Smuzhiyun if (rc > 0)
183*4882a593Smuzhiyun return 0;
184*4882a593Smuzhiyun /* At this point we know that the SINT pin is asserted, so we
185*4882a593Smuzhiyun * do not need to do i2c_nuvoton_check_status */
186*4882a593Smuzhiyun } else {
187*4882a593Smuzhiyun unsigned long ten_msec, stop;
188*4882a593Smuzhiyun bool status_valid;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* check current status */
191*4882a593Smuzhiyun status_valid = i2c_nuvoton_check_status(chip, mask, value);
192*4882a593Smuzhiyun if (status_valid)
193*4882a593Smuzhiyun return 0;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* use polling to wait for the event */
196*4882a593Smuzhiyun ten_msec = jiffies + usecs_to_jiffies(TPM_I2C_RETRY_DELAY_LONG);
197*4882a593Smuzhiyun stop = jiffies + timeout;
198*4882a593Smuzhiyun do {
199*4882a593Smuzhiyun if (time_before(jiffies, ten_msec))
200*4882a593Smuzhiyun usleep_range(TPM_I2C_RETRY_DELAY_SHORT,
201*4882a593Smuzhiyun TPM_I2C_RETRY_DELAY_SHORT
202*4882a593Smuzhiyun + TPM_I2C_DELAY_RANGE);
203*4882a593Smuzhiyun else
204*4882a593Smuzhiyun usleep_range(TPM_I2C_RETRY_DELAY_LONG,
205*4882a593Smuzhiyun TPM_I2C_RETRY_DELAY_LONG
206*4882a593Smuzhiyun + TPM_I2C_DELAY_RANGE);
207*4882a593Smuzhiyun status_valid = i2c_nuvoton_check_status(chip, mask,
208*4882a593Smuzhiyun value);
209*4882a593Smuzhiyun if (status_valid)
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun } while (time_before(jiffies, stop));
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun dev_err(&chip->dev, "%s(%02x, %02x) -> timeout\n", __func__, mask,
214*4882a593Smuzhiyun value);
215*4882a593Smuzhiyun return -ETIMEDOUT;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* wait for dataAvail field to be set in the TPM_STS register */
i2c_nuvoton_wait_for_data_avail(struct tpm_chip * chip,u32 timeout,wait_queue_head_t * queue)219*4882a593Smuzhiyun static int i2c_nuvoton_wait_for_data_avail(struct tpm_chip *chip, u32 timeout,
220*4882a593Smuzhiyun wait_queue_head_t *queue)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun return i2c_nuvoton_wait_for_stat(chip,
223*4882a593Smuzhiyun TPM_STS_DATA_AVAIL | TPM_STS_VALID,
224*4882a593Smuzhiyun TPM_STS_DATA_AVAIL | TPM_STS_VALID,
225*4882a593Smuzhiyun timeout, queue);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* Read @count bytes into @buf from TPM_RD_FIFO register */
i2c_nuvoton_recv_data(struct i2c_client * client,struct tpm_chip * chip,u8 * buf,size_t count)229*4882a593Smuzhiyun static int i2c_nuvoton_recv_data(struct i2c_client *client,
230*4882a593Smuzhiyun struct tpm_chip *chip, u8 *buf, size_t count)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun struct priv_data *priv = dev_get_drvdata(&chip->dev);
233*4882a593Smuzhiyun s32 rc;
234*4882a593Smuzhiyun int burst_count, bytes2read, size = 0;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun while (size < count &&
237*4882a593Smuzhiyun i2c_nuvoton_wait_for_data_avail(chip,
238*4882a593Smuzhiyun chip->timeout_c,
239*4882a593Smuzhiyun &priv->read_queue) == 0) {
240*4882a593Smuzhiyun burst_count = i2c_nuvoton_get_burstcount(client, chip);
241*4882a593Smuzhiyun if (burst_count < 0) {
242*4882a593Smuzhiyun dev_err(&chip->dev,
243*4882a593Smuzhiyun "%s() fail to read burstCount=%d\n", __func__,
244*4882a593Smuzhiyun burst_count);
245*4882a593Smuzhiyun return -EIO;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun bytes2read = min_t(size_t, burst_count, count - size);
248*4882a593Smuzhiyun rc = i2c_nuvoton_read_buf(client, TPM_DATA_FIFO_R,
249*4882a593Smuzhiyun bytes2read, &buf[size]);
250*4882a593Smuzhiyun if (rc < 0) {
251*4882a593Smuzhiyun dev_err(&chip->dev,
252*4882a593Smuzhiyun "%s() fail on i2c_nuvoton_read_buf()=%d\n",
253*4882a593Smuzhiyun __func__, rc);
254*4882a593Smuzhiyun return -EIO;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun dev_dbg(&chip->dev, "%s(%d):", __func__, bytes2read);
257*4882a593Smuzhiyun size += bytes2read;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return size;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /* Read TPM command results */
i2c_nuvoton_recv(struct tpm_chip * chip,u8 * buf,size_t count)264*4882a593Smuzhiyun static int i2c_nuvoton_recv(struct tpm_chip *chip, u8 *buf, size_t count)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun struct priv_data *priv = dev_get_drvdata(&chip->dev);
267*4882a593Smuzhiyun struct device *dev = chip->dev.parent;
268*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
269*4882a593Smuzhiyun s32 rc;
270*4882a593Smuzhiyun int status;
271*4882a593Smuzhiyun int burst_count;
272*4882a593Smuzhiyun int retries;
273*4882a593Smuzhiyun int size = 0;
274*4882a593Smuzhiyun u32 expected;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (count < TPM_HEADER_SIZE) {
277*4882a593Smuzhiyun i2c_nuvoton_ready(chip); /* return to idle */
278*4882a593Smuzhiyun dev_err(dev, "%s() count < header size\n", __func__);
279*4882a593Smuzhiyun return -EIO;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun for (retries = 0; retries < TPM_I2C_RETRIES; retries++) {
282*4882a593Smuzhiyun if (retries > 0) {
283*4882a593Smuzhiyun /* if this is not the first trial, set responseRetry */
284*4882a593Smuzhiyun i2c_nuvoton_write_status(client,
285*4882a593Smuzhiyun TPM_STS_RESPONSE_RETRY);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun /*
288*4882a593Smuzhiyun * read first available (> 10 bytes), including:
289*4882a593Smuzhiyun * tag, paramsize, and result
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun status = i2c_nuvoton_wait_for_data_avail(
292*4882a593Smuzhiyun chip, chip->timeout_c, &priv->read_queue);
293*4882a593Smuzhiyun if (status != 0) {
294*4882a593Smuzhiyun dev_err(dev, "%s() timeout on dataAvail\n", __func__);
295*4882a593Smuzhiyun size = -ETIMEDOUT;
296*4882a593Smuzhiyun continue;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun burst_count = i2c_nuvoton_get_burstcount(client, chip);
299*4882a593Smuzhiyun if (burst_count < 0) {
300*4882a593Smuzhiyun dev_err(dev, "%s() fail to get burstCount\n", __func__);
301*4882a593Smuzhiyun size = -EIO;
302*4882a593Smuzhiyun continue;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun size = i2c_nuvoton_recv_data(client, chip, buf,
305*4882a593Smuzhiyun burst_count);
306*4882a593Smuzhiyun if (size < TPM_HEADER_SIZE) {
307*4882a593Smuzhiyun dev_err(dev, "%s() fail to read header\n", __func__);
308*4882a593Smuzhiyun size = -EIO;
309*4882a593Smuzhiyun continue;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun /*
312*4882a593Smuzhiyun * convert number of expected bytes field from big endian 32 bit
313*4882a593Smuzhiyun * to machine native
314*4882a593Smuzhiyun */
315*4882a593Smuzhiyun expected = be32_to_cpu(*(__be32 *) (buf + 2));
316*4882a593Smuzhiyun if (expected > count || expected < size) {
317*4882a593Smuzhiyun dev_err(dev, "%s() expected > count\n", __func__);
318*4882a593Smuzhiyun size = -EIO;
319*4882a593Smuzhiyun continue;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun rc = i2c_nuvoton_recv_data(client, chip, &buf[size],
322*4882a593Smuzhiyun expected - size);
323*4882a593Smuzhiyun size += rc;
324*4882a593Smuzhiyun if (rc < 0 || size < expected) {
325*4882a593Smuzhiyun dev_err(dev, "%s() fail to read remainder of result\n",
326*4882a593Smuzhiyun __func__);
327*4882a593Smuzhiyun size = -EIO;
328*4882a593Smuzhiyun continue;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun if (i2c_nuvoton_wait_for_stat(
331*4882a593Smuzhiyun chip, TPM_STS_VALID | TPM_STS_DATA_AVAIL,
332*4882a593Smuzhiyun TPM_STS_VALID, chip->timeout_c,
333*4882a593Smuzhiyun NULL)) {
334*4882a593Smuzhiyun dev_err(dev, "%s() error left over data\n", __func__);
335*4882a593Smuzhiyun size = -ETIMEDOUT;
336*4882a593Smuzhiyun continue;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun break;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
341*4882a593Smuzhiyun dev_dbg(&chip->dev, "%s() -> %d\n", __func__, size);
342*4882a593Smuzhiyun return size;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /*
346*4882a593Smuzhiyun * Send TPM command.
347*4882a593Smuzhiyun *
348*4882a593Smuzhiyun * If interrupts are used (signaled by an irq set in the vendor structure)
349*4882a593Smuzhiyun * tpm.c can skip polling for the data to be available as the interrupt is
350*4882a593Smuzhiyun * waited for here
351*4882a593Smuzhiyun */
i2c_nuvoton_send(struct tpm_chip * chip,u8 * buf,size_t len)352*4882a593Smuzhiyun static int i2c_nuvoton_send(struct tpm_chip *chip, u8 *buf, size_t len)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct priv_data *priv = dev_get_drvdata(&chip->dev);
355*4882a593Smuzhiyun struct device *dev = chip->dev.parent;
356*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
357*4882a593Smuzhiyun u32 ordinal;
358*4882a593Smuzhiyun unsigned long duration;
359*4882a593Smuzhiyun size_t count = 0;
360*4882a593Smuzhiyun int burst_count, bytes2write, retries, rc = -EIO;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun for (retries = 0; retries < TPM_RETRY; retries++) {
363*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
364*4882a593Smuzhiyun if (i2c_nuvoton_wait_for_stat(chip, TPM_STS_COMMAND_READY,
365*4882a593Smuzhiyun TPM_STS_COMMAND_READY,
366*4882a593Smuzhiyun chip->timeout_b, NULL)) {
367*4882a593Smuzhiyun dev_err(dev, "%s() timeout on commandReady\n",
368*4882a593Smuzhiyun __func__);
369*4882a593Smuzhiyun rc = -EIO;
370*4882a593Smuzhiyun continue;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun rc = 0;
373*4882a593Smuzhiyun while (count < len - 1) {
374*4882a593Smuzhiyun burst_count = i2c_nuvoton_get_burstcount(client,
375*4882a593Smuzhiyun chip);
376*4882a593Smuzhiyun if (burst_count < 0) {
377*4882a593Smuzhiyun dev_err(dev, "%s() fail get burstCount\n",
378*4882a593Smuzhiyun __func__);
379*4882a593Smuzhiyun rc = -EIO;
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun bytes2write = min_t(size_t, burst_count,
383*4882a593Smuzhiyun len - 1 - count);
384*4882a593Smuzhiyun rc = i2c_nuvoton_write_buf(client, TPM_DATA_FIFO_W,
385*4882a593Smuzhiyun bytes2write, &buf[count]);
386*4882a593Smuzhiyun if (rc < 0) {
387*4882a593Smuzhiyun dev_err(dev, "%s() fail i2cWriteBuf\n",
388*4882a593Smuzhiyun __func__);
389*4882a593Smuzhiyun break;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun dev_dbg(dev, "%s(%d):", __func__, bytes2write);
392*4882a593Smuzhiyun count += bytes2write;
393*4882a593Smuzhiyun rc = i2c_nuvoton_wait_for_stat(chip,
394*4882a593Smuzhiyun TPM_STS_VALID |
395*4882a593Smuzhiyun TPM_STS_EXPECT,
396*4882a593Smuzhiyun TPM_STS_VALID |
397*4882a593Smuzhiyun TPM_STS_EXPECT,
398*4882a593Smuzhiyun chip->timeout_c,
399*4882a593Smuzhiyun NULL);
400*4882a593Smuzhiyun if (rc < 0) {
401*4882a593Smuzhiyun dev_err(dev, "%s() timeout on Expect\n",
402*4882a593Smuzhiyun __func__);
403*4882a593Smuzhiyun rc = -ETIMEDOUT;
404*4882a593Smuzhiyun break;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun if (rc < 0)
408*4882a593Smuzhiyun continue;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* write last byte */
411*4882a593Smuzhiyun rc = i2c_nuvoton_write_buf(client, TPM_DATA_FIFO_W, 1,
412*4882a593Smuzhiyun &buf[count]);
413*4882a593Smuzhiyun if (rc < 0) {
414*4882a593Smuzhiyun dev_err(dev, "%s() fail to write last byte\n",
415*4882a593Smuzhiyun __func__);
416*4882a593Smuzhiyun rc = -EIO;
417*4882a593Smuzhiyun continue;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun dev_dbg(dev, "%s(last): %02x", __func__, buf[count]);
420*4882a593Smuzhiyun rc = i2c_nuvoton_wait_for_stat(chip,
421*4882a593Smuzhiyun TPM_STS_VALID | TPM_STS_EXPECT,
422*4882a593Smuzhiyun TPM_STS_VALID,
423*4882a593Smuzhiyun chip->timeout_c, NULL);
424*4882a593Smuzhiyun if (rc) {
425*4882a593Smuzhiyun dev_err(dev, "%s() timeout on Expect to clear\n",
426*4882a593Smuzhiyun __func__);
427*4882a593Smuzhiyun rc = -ETIMEDOUT;
428*4882a593Smuzhiyun continue;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun break;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun if (rc < 0) {
433*4882a593Smuzhiyun /* retries == TPM_RETRY */
434*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
435*4882a593Smuzhiyun return rc;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun /* execute the TPM command */
438*4882a593Smuzhiyun rc = i2c_nuvoton_write_status(client, TPM_STS_GO);
439*4882a593Smuzhiyun if (rc < 0) {
440*4882a593Smuzhiyun dev_err(dev, "%s() fail to write Go\n", __func__);
441*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
442*4882a593Smuzhiyun return rc;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
445*4882a593Smuzhiyun duration = tpm_calc_ordinal_duration(chip, ordinal);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun rc = i2c_nuvoton_wait_for_data_avail(chip, duration, &priv->read_queue);
448*4882a593Smuzhiyun if (rc) {
449*4882a593Smuzhiyun dev_err(dev, "%s() timeout command duration %ld\n",
450*4882a593Smuzhiyun __func__, duration);
451*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
452*4882a593Smuzhiyun return rc;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun dev_dbg(dev, "%s() -> %zd\n", __func__, len);
456*4882a593Smuzhiyun return 0;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
i2c_nuvoton_req_canceled(struct tpm_chip * chip,u8 status)459*4882a593Smuzhiyun static bool i2c_nuvoton_req_canceled(struct tpm_chip *chip, u8 status)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun return (status == TPM_STS_COMMAND_READY);
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun static const struct tpm_class_ops tpm_i2c = {
465*4882a593Smuzhiyun .flags = TPM_OPS_AUTO_STARTUP,
466*4882a593Smuzhiyun .status = i2c_nuvoton_read_status,
467*4882a593Smuzhiyun .recv = i2c_nuvoton_recv,
468*4882a593Smuzhiyun .send = i2c_nuvoton_send,
469*4882a593Smuzhiyun .cancel = i2c_nuvoton_ready,
470*4882a593Smuzhiyun .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
471*4882a593Smuzhiyun .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
472*4882a593Smuzhiyun .req_canceled = i2c_nuvoton_req_canceled,
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* The only purpose for the handler is to signal to any waiting threads that
476*4882a593Smuzhiyun * the interrupt is currently being asserted. The driver does not do any
477*4882a593Smuzhiyun * processing triggered by interrupts, and the chip provides no way to mask at
478*4882a593Smuzhiyun * the source (plus that would be slow over I2C). Run the IRQ as a one-shot,
479*4882a593Smuzhiyun * this means it cannot be shared. */
i2c_nuvoton_int_handler(int dummy,void * dev_id)480*4882a593Smuzhiyun static irqreturn_t i2c_nuvoton_int_handler(int dummy, void *dev_id)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct tpm_chip *chip = dev_id;
483*4882a593Smuzhiyun struct priv_data *priv = dev_get_drvdata(&chip->dev);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun priv->intrs++;
486*4882a593Smuzhiyun wake_up(&priv->read_queue);
487*4882a593Smuzhiyun disable_irq_nosync(priv->irq);
488*4882a593Smuzhiyun return IRQ_HANDLED;
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun
get_vid(struct i2c_client * client,u32 * res)491*4882a593Smuzhiyun static int get_vid(struct i2c_client *client, u32 *res)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun static const u8 vid_did_rid_value[] = { 0x50, 0x10, 0xfe };
494*4882a593Smuzhiyun u32 temp;
495*4882a593Smuzhiyun s32 rc;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
498*4882a593Smuzhiyun return -ENODEV;
499*4882a593Smuzhiyun rc = i2c_nuvoton_read_buf(client, TPM_VID_DID_RID, 4, (u8 *)&temp);
500*4882a593Smuzhiyun if (rc < 0)
501*4882a593Smuzhiyun return rc;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* check WPCT301 values - ignore RID */
504*4882a593Smuzhiyun if (memcmp(&temp, vid_did_rid_value, sizeof(vid_did_rid_value))) {
505*4882a593Smuzhiyun /*
506*4882a593Smuzhiyun * f/w rev 2.81 has an issue where the VID_DID_RID is not
507*4882a593Smuzhiyun * reporting the right value. so give it another chance at
508*4882a593Smuzhiyun * offset 0x20 (FIFO_W).
509*4882a593Smuzhiyun */
510*4882a593Smuzhiyun rc = i2c_nuvoton_read_buf(client, TPM_DATA_FIFO_W, 4,
511*4882a593Smuzhiyun (u8 *) (&temp));
512*4882a593Smuzhiyun if (rc < 0)
513*4882a593Smuzhiyun return rc;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun /* check WPCT301 values - ignore RID */
516*4882a593Smuzhiyun if (memcmp(&temp, vid_did_rid_value,
517*4882a593Smuzhiyun sizeof(vid_did_rid_value)))
518*4882a593Smuzhiyun return -ENODEV;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun *res = temp;
522*4882a593Smuzhiyun return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
i2c_nuvoton_probe(struct i2c_client * client,const struct i2c_device_id * id)525*4882a593Smuzhiyun static int i2c_nuvoton_probe(struct i2c_client *client,
526*4882a593Smuzhiyun const struct i2c_device_id *id)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun int rc;
529*4882a593Smuzhiyun struct tpm_chip *chip;
530*4882a593Smuzhiyun struct device *dev = &client->dev;
531*4882a593Smuzhiyun struct priv_data *priv;
532*4882a593Smuzhiyun u32 vid = 0;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun rc = get_vid(client, &vid);
535*4882a593Smuzhiyun if (rc)
536*4882a593Smuzhiyun return rc;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun dev_info(dev, "VID: %04X DID: %02X RID: %02X\n", (u16) vid,
539*4882a593Smuzhiyun (u8) (vid >> 16), (u8) (vid >> 24));
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun chip = tpmm_chip_alloc(dev, &tpm_i2c);
542*4882a593Smuzhiyun if (IS_ERR(chip))
543*4882a593Smuzhiyun return PTR_ERR(chip);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
546*4882a593Smuzhiyun if (!priv)
547*4882a593Smuzhiyun return -ENOMEM;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if (dev->of_node) {
550*4882a593Smuzhiyun const struct of_device_id *of_id;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun of_id = of_match_device(dev->driver->of_match_table, dev);
553*4882a593Smuzhiyun if (of_id && of_id->data == OF_IS_TPM2)
554*4882a593Smuzhiyun chip->flags |= TPM_CHIP_FLAG_TPM2;
555*4882a593Smuzhiyun } else
556*4882a593Smuzhiyun if (id->driver_data == I2C_IS_TPM2)
557*4882a593Smuzhiyun chip->flags |= TPM_CHIP_FLAG_TPM2;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun init_waitqueue_head(&priv->read_queue);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun /* Default timeouts */
562*4882a593Smuzhiyun chip->timeout_a = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
563*4882a593Smuzhiyun chip->timeout_b = msecs_to_jiffies(TPM_I2C_LONG_TIMEOUT);
564*4882a593Smuzhiyun chip->timeout_c = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
565*4882a593Smuzhiyun chip->timeout_d = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun dev_set_drvdata(&chip->dev, priv);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun /*
570*4882a593Smuzhiyun * I2C intfcaps (interrupt capabilitieis) in the chip are hard coded to:
571*4882a593Smuzhiyun * TPM_INTF_INT_LEVEL_LOW | TPM_INTF_DATA_AVAIL_INT
572*4882a593Smuzhiyun * The IRQ should be set in the i2c_board_info (which is done
573*4882a593Smuzhiyun * automatically in of_i2c_register_devices, for device tree users */
574*4882a593Smuzhiyun priv->irq = client->irq;
575*4882a593Smuzhiyun if (client->irq) {
576*4882a593Smuzhiyun dev_dbg(dev, "%s() priv->irq\n", __func__);
577*4882a593Smuzhiyun rc = devm_request_irq(dev, client->irq,
578*4882a593Smuzhiyun i2c_nuvoton_int_handler,
579*4882a593Smuzhiyun IRQF_TRIGGER_LOW,
580*4882a593Smuzhiyun dev_name(&chip->dev),
581*4882a593Smuzhiyun chip);
582*4882a593Smuzhiyun if (rc) {
583*4882a593Smuzhiyun dev_err(dev, "%s() Unable to request irq: %d for use\n",
584*4882a593Smuzhiyun __func__, priv->irq);
585*4882a593Smuzhiyun priv->irq = 0;
586*4882a593Smuzhiyun } else {
587*4882a593Smuzhiyun chip->flags |= TPM_CHIP_FLAG_IRQ;
588*4882a593Smuzhiyun /* Clear any pending interrupt */
589*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
590*4882a593Smuzhiyun /* - wait for TPM_STS==0xA0 (stsValid, commandReady) */
591*4882a593Smuzhiyun rc = i2c_nuvoton_wait_for_stat(chip,
592*4882a593Smuzhiyun TPM_STS_COMMAND_READY,
593*4882a593Smuzhiyun TPM_STS_COMMAND_READY,
594*4882a593Smuzhiyun chip->timeout_b,
595*4882a593Smuzhiyun NULL);
596*4882a593Smuzhiyun if (rc == 0) {
597*4882a593Smuzhiyun /*
598*4882a593Smuzhiyun * TIS is in ready state
599*4882a593Smuzhiyun * write dummy byte to enter reception state
600*4882a593Smuzhiyun * TPM_DATA_FIFO_W <- rc (0)
601*4882a593Smuzhiyun */
602*4882a593Smuzhiyun rc = i2c_nuvoton_write_buf(client,
603*4882a593Smuzhiyun TPM_DATA_FIFO_W,
604*4882a593Smuzhiyun 1, (u8 *) (&rc));
605*4882a593Smuzhiyun if (rc < 0)
606*4882a593Smuzhiyun return rc;
607*4882a593Smuzhiyun /* TPM_STS <- 0x40 (commandReady) */
608*4882a593Smuzhiyun i2c_nuvoton_ready(chip);
609*4882a593Smuzhiyun } else {
610*4882a593Smuzhiyun /*
611*4882a593Smuzhiyun * timeout_b reached - command was
612*4882a593Smuzhiyun * aborted. TIS should now be in idle state -
613*4882a593Smuzhiyun * only TPM_STS_VALID should be set
614*4882a593Smuzhiyun */
615*4882a593Smuzhiyun if (i2c_nuvoton_read_status(chip) !=
616*4882a593Smuzhiyun TPM_STS_VALID)
617*4882a593Smuzhiyun return -EIO;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun return tpm_chip_register(chip);
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
i2c_nuvoton_remove(struct i2c_client * client)625*4882a593Smuzhiyun static int i2c_nuvoton_remove(struct i2c_client *client)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun struct tpm_chip *chip = i2c_get_clientdata(client);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun tpm_chip_unregister(chip);
630*4882a593Smuzhiyun return 0;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun static const struct i2c_device_id i2c_nuvoton_id[] = {
634*4882a593Smuzhiyun {"tpm_i2c_nuvoton"},
635*4882a593Smuzhiyun {"tpm2_i2c_nuvoton", .driver_data = I2C_IS_TPM2},
636*4882a593Smuzhiyun {}
637*4882a593Smuzhiyun };
638*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, i2c_nuvoton_id);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun #ifdef CONFIG_OF
641*4882a593Smuzhiyun static const struct of_device_id i2c_nuvoton_of_match[] = {
642*4882a593Smuzhiyun {.compatible = "nuvoton,npct501"},
643*4882a593Smuzhiyun {.compatible = "winbond,wpct301"},
644*4882a593Smuzhiyun {.compatible = "nuvoton,npct601", .data = OF_IS_TPM2},
645*4882a593Smuzhiyun {},
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, i2c_nuvoton_of_match);
648*4882a593Smuzhiyun #endif
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(i2c_nuvoton_pm_ops, tpm_pm_suspend, tpm_pm_resume);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun static struct i2c_driver i2c_nuvoton_driver = {
653*4882a593Smuzhiyun .id_table = i2c_nuvoton_id,
654*4882a593Smuzhiyun .probe = i2c_nuvoton_probe,
655*4882a593Smuzhiyun .remove = i2c_nuvoton_remove,
656*4882a593Smuzhiyun .driver = {
657*4882a593Smuzhiyun .name = "tpm_i2c_nuvoton",
658*4882a593Smuzhiyun .pm = &i2c_nuvoton_pm_ops,
659*4882a593Smuzhiyun .of_match_table = of_match_ptr(i2c_nuvoton_of_match),
660*4882a593Smuzhiyun },
661*4882a593Smuzhiyun };
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun module_i2c_driver(i2c_nuvoton_driver);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun MODULE_AUTHOR("Dan Morav (dan.morav@nuvoton.com)");
666*4882a593Smuzhiyun MODULE_DESCRIPTION("Nuvoton TPM I2C Driver");
667*4882a593Smuzhiyun MODULE_LICENSE("GPL");
668