1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2005 IBM Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Kylene Hall <kjhall@us.ibm.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Maintained by: <tpmdd-devel@lists.sourceforge.net>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Device driver for TCG/TCPA TPM (trusted platform module).
11*4882a593Smuzhiyun * Specifications at www.trustedcomputinggroup.org
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * These difference are required on power because the device must be
14*4882a593Smuzhiyun * discovered through the device tree and iomap must be used to get
15*4882a593Smuzhiyun * around the need for holes in the io_page_mask. This does not happen
16*4882a593Smuzhiyun * automatically because the tpm is not a normal pci device and lives
17*4882a593Smuzhiyun * under the root node.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct tpm_atmel_priv {
21*4882a593Smuzhiyun int region_size;
22*4882a593Smuzhiyun int have_region;
23*4882a593Smuzhiyun unsigned long base;
24*4882a593Smuzhiyun void __iomem *iobase;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #ifdef CONFIG_PPC64
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <asm/prom.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define atmel_getb(priv, offset) readb(priv->iobase + offset)
32*4882a593Smuzhiyun #define atmel_putb(val, priv, offset) writeb(val, priv->iobase + offset)
33*4882a593Smuzhiyun #define atmel_request_region request_mem_region
34*4882a593Smuzhiyun #define atmel_release_region release_mem_region
35*4882a593Smuzhiyun
atmel_put_base_addr(void __iomem * iobase)36*4882a593Smuzhiyun static inline void atmel_put_base_addr(void __iomem *iobase)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun iounmap(iobase);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
atmel_get_base_addr(unsigned long * base,int * region_size)41*4882a593Smuzhiyun static void __iomem * atmel_get_base_addr(unsigned long *base, int *region_size)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct device_node *dn;
44*4882a593Smuzhiyun unsigned long address, size;
45*4882a593Smuzhiyun const unsigned int *reg;
46*4882a593Smuzhiyun int reglen;
47*4882a593Smuzhiyun int naddrc;
48*4882a593Smuzhiyun int nsizec;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun dn = of_find_node_by_name(NULL, "tpm");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (!dn)
53*4882a593Smuzhiyun return NULL;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (!of_device_is_compatible(dn, "AT97SC3201")) {
56*4882a593Smuzhiyun of_node_put(dn);
57*4882a593Smuzhiyun return NULL;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun reg = of_get_property(dn, "reg", ®len);
61*4882a593Smuzhiyun naddrc = of_n_addr_cells(dn);
62*4882a593Smuzhiyun nsizec = of_n_size_cells(dn);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun of_node_put(dn);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (naddrc == 2)
68*4882a593Smuzhiyun address = ((unsigned long) reg[0] << 32) | reg[1];
69*4882a593Smuzhiyun else
70*4882a593Smuzhiyun address = reg[0];
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (nsizec == 2)
73*4882a593Smuzhiyun size =
74*4882a593Smuzhiyun ((unsigned long) reg[naddrc] << 32) | reg[naddrc + 1];
75*4882a593Smuzhiyun else
76*4882a593Smuzhiyun size = reg[naddrc];
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun *base = address;
79*4882a593Smuzhiyun *region_size = size;
80*4882a593Smuzhiyun return ioremap(*base, *region_size);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun #else
83*4882a593Smuzhiyun #define atmel_getb(chip, offset) inb(atmel_get_priv(chip)->base + offset)
84*4882a593Smuzhiyun #define atmel_putb(val, chip, offset) \
85*4882a593Smuzhiyun outb(val, atmel_get_priv(chip)->base + offset)
86*4882a593Smuzhiyun #define atmel_request_region request_region
87*4882a593Smuzhiyun #define atmel_release_region release_region
88*4882a593Smuzhiyun /* Atmel definitions */
89*4882a593Smuzhiyun enum tpm_atmel_addr {
90*4882a593Smuzhiyun TPM_ATMEL_BASE_ADDR_LO = 0x08,
91*4882a593Smuzhiyun TPM_ATMEL_BASE_ADDR_HI = 0x09
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
tpm_read_index(int base,int index)94*4882a593Smuzhiyun static inline int tpm_read_index(int base, int index)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun outb(index, base);
97*4882a593Smuzhiyun return inb(base+1) & 0xFF;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Verify this is a 1.1 Atmel TPM */
atmel_verify_tpm11(void)101*4882a593Smuzhiyun static int atmel_verify_tpm11(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* verify that it is an Atmel part */
105*4882a593Smuzhiyun if (tpm_read_index(TPM_ADDR, 4) != 'A' ||
106*4882a593Smuzhiyun tpm_read_index(TPM_ADDR, 5) != 'T' ||
107*4882a593Smuzhiyun tpm_read_index(TPM_ADDR, 6) != 'M' ||
108*4882a593Smuzhiyun tpm_read_index(TPM_ADDR, 7) != 'L')
109*4882a593Smuzhiyun return 1;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* query chip for its version number */
112*4882a593Smuzhiyun if (tpm_read_index(TPM_ADDR, 0x00) != 1 ||
113*4882a593Smuzhiyun tpm_read_index(TPM_ADDR, 0x01) != 1)
114*4882a593Smuzhiyun return 1;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* This is an atmel supported part */
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
atmel_put_base_addr(void __iomem * iobase)120*4882a593Smuzhiyun static inline void atmel_put_base_addr(void __iomem *iobase)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Determine where to talk to device */
atmel_get_base_addr(unsigned long * base,int * region_size)125*4882a593Smuzhiyun static void __iomem * atmel_get_base_addr(unsigned long *base, int *region_size)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun int lo, hi;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (atmel_verify_tpm11() != 0)
130*4882a593Smuzhiyun return NULL;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun lo = tpm_read_index(TPM_ADDR, TPM_ATMEL_BASE_ADDR_LO);
133*4882a593Smuzhiyun hi = tpm_read_index(TPM_ADDR, TPM_ATMEL_BASE_ADDR_HI);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun *base = (hi << 8) | lo;
136*4882a593Smuzhiyun *region_size = 2;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return ioport_map(*base, *region_size);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun #endif
141