1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * tp3780i.c -- board driver for 3780i on ThinkPads
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Written By: Mike Sullivan IBM Corporation
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 1999 IBM Corporation
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
11*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by
12*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or
13*4882a593Smuzhiyun * (at your option) any later version.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful,
16*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18*4882a593Smuzhiyun * GNU General Public License for more details.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * NO WARRANTY
21*4882a593Smuzhiyun * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22*4882a593Smuzhiyun * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23*4882a593Smuzhiyun * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24*4882a593Smuzhiyun * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25*4882a593Smuzhiyun * solely responsible for determining the appropriateness of using and
26*4882a593Smuzhiyun * distributing the Program and assumes all risks associated with its
27*4882a593Smuzhiyun * exercise of rights under this Agreement, including but not limited to
28*4882a593Smuzhiyun * the risks and costs of program errors, damage to or loss of data,
29*4882a593Smuzhiyun * programs or equipment, and unavailability or interruption of operations.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * DISCLAIMER OF LIABILITY
32*4882a593Smuzhiyun * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34*4882a593Smuzhiyun * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36*4882a593Smuzhiyun * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37*4882a593Smuzhiyun * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38*4882a593Smuzhiyun * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
41*4882a593Smuzhiyun * along with this program; if not, write to the Free Software
42*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * 10/23/2000 - Alpha Release
46*4882a593Smuzhiyun * First release to the public
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <linux/interrupt.h>
50*4882a593Smuzhiyun #include <linux/kernel.h>
51*4882a593Smuzhiyun #include <linux/ptrace.h>
52*4882a593Smuzhiyun #include <linux/ioport.h>
53*4882a593Smuzhiyun #include <asm/io.h>
54*4882a593Smuzhiyun #include "smapi.h"
55*4882a593Smuzhiyun #include "mwavedd.h"
56*4882a593Smuzhiyun #include "tp3780i.h"
57*4882a593Smuzhiyun #include "3780i.h"
58*4882a593Smuzhiyun #include "mwavepub.h"
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static unsigned short s_ausThinkpadIrqToField[16] =
61*4882a593Smuzhiyun { 0xFFFF, 0xFFFF, 0xFFFF, 0x0001, 0x0002, 0x0003, 0xFFFF, 0x0004,
62*4882a593Smuzhiyun 0xFFFF, 0xFFFF, 0x0005, 0x0006, 0xFFFF, 0xFFFF, 0xFFFF, 0x0007 };
63*4882a593Smuzhiyun static unsigned short s_ausThinkpadDmaToField[8] =
64*4882a593Smuzhiyun { 0x0001, 0x0002, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0003, 0x0004 };
65*4882a593Smuzhiyun static unsigned short s_numIrqs = 16, s_numDmas = 8;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun
EnableSRAM(THINKPAD_BD_DATA * pBDData)68*4882a593Smuzhiyun static void EnableSRAM(THINKPAD_BD_DATA * pBDData)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
71*4882a593Smuzhiyun unsigned short usDspBaseIO = pSettings->usDspBaseIO;
72*4882a593Smuzhiyun DSP_GPIO_OUTPUT_DATA_15_8 rGpioOutputData;
73*4882a593Smuzhiyun DSP_GPIO_DRIVER_ENABLE_15_8 rGpioDriverEnable;
74*4882a593Smuzhiyun DSP_GPIO_MODE_15_8 rGpioMode;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM, entry\n");
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun MKWORD(rGpioMode) = ReadMsaCfg(DSP_GpioModeControl_15_8);
79*4882a593Smuzhiyun rGpioMode.GpioMode10 = 0;
80*4882a593Smuzhiyun WriteMsaCfg(DSP_GpioModeControl_15_8, MKWORD(rGpioMode));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun MKWORD(rGpioDriverEnable) = 0;
83*4882a593Smuzhiyun rGpioDriverEnable.Enable10 = true;
84*4882a593Smuzhiyun rGpioDriverEnable.Mask10 = true;
85*4882a593Smuzhiyun WriteMsaCfg(DSP_GpioDriverEnable_15_8, MKWORD(rGpioDriverEnable));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun MKWORD(rGpioOutputData) = 0;
88*4882a593Smuzhiyun rGpioOutputData.Latch10 = 0;
89*4882a593Smuzhiyun rGpioOutputData.Mask10 = true;
90*4882a593Smuzhiyun WriteMsaCfg(DSP_GpioOutputData_15_8, MKWORD(rGpioOutputData));
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM exit\n");
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
UartInterrupt(int irq,void * dev_id)96*4882a593Smuzhiyun static irqreturn_t UartInterrupt(int irq, void *dev_id)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun PRINTK_3(TRACE_TP3780I,
99*4882a593Smuzhiyun "tp3780i::UartInterrupt entry irq %x dev_id %p\n", irq, dev_id);
100*4882a593Smuzhiyun return IRQ_HANDLED;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
DspInterrupt(int irq,void * dev_id)103*4882a593Smuzhiyun static irqreturn_t DspInterrupt(int irq, void *dev_id)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
106*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pDrvData->rBDData.rDspSettings;
107*4882a593Smuzhiyun unsigned short usDspBaseIO = pSettings->usDspBaseIO;
108*4882a593Smuzhiyun unsigned short usIPCSource = 0, usIsolationMask, usPCNum;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun PRINTK_3(TRACE_TP3780I,
111*4882a593Smuzhiyun "tp3780i::DspInterrupt entry irq %x dev_id %p\n", irq, dev_id);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (dsp3780I_GetIPCSource(usDspBaseIO, &usIPCSource) == 0) {
114*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
115*4882a593Smuzhiyun "tp3780i::DspInterrupt, return from dsp3780i_GetIPCSource, usIPCSource %x\n",
116*4882a593Smuzhiyun usIPCSource);
117*4882a593Smuzhiyun usIsolationMask = 1;
118*4882a593Smuzhiyun for (usPCNum = 1; usPCNum <= 16; usPCNum++) {
119*4882a593Smuzhiyun if (usIPCSource & usIsolationMask) {
120*4882a593Smuzhiyun usIPCSource &= ~usIsolationMask;
121*4882a593Smuzhiyun PRINTK_3(TRACE_TP3780I,
122*4882a593Smuzhiyun "tp3780i::DspInterrupt usPCNum %x usIPCSource %x\n",
123*4882a593Smuzhiyun usPCNum, usIPCSource);
124*4882a593Smuzhiyun if (pDrvData->IPCs[usPCNum - 1].usIntCount == 0) {
125*4882a593Smuzhiyun pDrvData->IPCs[usPCNum - 1].usIntCount = 1;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
128*4882a593Smuzhiyun "tp3780i::DspInterrupt usIntCount %x\n",
129*4882a593Smuzhiyun pDrvData->IPCs[usPCNum - 1].usIntCount);
130*4882a593Smuzhiyun if (pDrvData->IPCs[usPCNum - 1].bIsEnabled == true) {
131*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
132*4882a593Smuzhiyun "tp3780i::DspInterrupt, waking up usPCNum %x\n",
133*4882a593Smuzhiyun usPCNum - 1);
134*4882a593Smuzhiyun wake_up_interruptible(&pDrvData->IPCs[usPCNum - 1].ipc_wait_queue);
135*4882a593Smuzhiyun } else {
136*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
137*4882a593Smuzhiyun "tp3780i::DspInterrupt, no one waiting for IPC %x\n",
138*4882a593Smuzhiyun usPCNum - 1);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun if (usIPCSource == 0)
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun /* try next IPC */
144*4882a593Smuzhiyun usIsolationMask = usIsolationMask << 1;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun } else {
147*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I,
148*4882a593Smuzhiyun "tp3780i::DspInterrupt, return false from dsp3780i_GetIPCSource\n");
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I, "tp3780i::DspInterrupt exit\n");
151*4882a593Smuzhiyun return IRQ_HANDLED;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun
tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData)155*4882a593Smuzhiyun int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun int retval = 0;
158*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData entry pBDData %p\n", pBDData);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun pBDData->bDSPEnabled = false;
164*4882a593Smuzhiyun pSettings->bInterruptClaimed = false;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun retval = smapi_init();
167*4882a593Smuzhiyun if (retval) {
168*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_InitializeBoardData: Error: SMAPI is not available on this machine\n");
169*4882a593Smuzhiyun } else {
170*4882a593Smuzhiyun if (mwave_3780i_irq || mwave_3780i_io || mwave_uart_irq || mwave_uart_io) {
171*4882a593Smuzhiyun retval = smapi_set_DSP_cfg();
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData exit retval %x\n", retval);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun return retval;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
tp3780I_Cleanup(THINKPAD_BD_DATA * pBDData)180*4882a593Smuzhiyun int tp3780I_Cleanup(THINKPAD_BD_DATA * pBDData)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun int retval = 0;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
185*4882a593Smuzhiyun "tp3780i::tp3780I_Cleanup entry and exit pBDData %p\n", pBDData);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return retval;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData)190*4882a593Smuzhiyun int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun SMAPI_DSP_SETTINGS rSmapiInfo;
193*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
196*4882a593Smuzhiyun "tp3780i::tp3780I_CalcResources entry pBDData %p\n", pBDData);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (smapi_query_DSP_cfg(&rSmapiInfo)) {
199*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Could not query DSP config. Aborting.\n");
200*4882a593Smuzhiyun return -EIO;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* Sanity check */
204*4882a593Smuzhiyun if (
205*4882a593Smuzhiyun ( rSmapiInfo.usDspIRQ == 0 )
206*4882a593Smuzhiyun || ( rSmapiInfo.usDspBaseIO == 0 )
207*4882a593Smuzhiyun || ( rSmapiInfo.usUartIRQ == 0 )
208*4882a593Smuzhiyun || ( rSmapiInfo.usUartBaseIO == 0 )
209*4882a593Smuzhiyun ) {
210*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Illegal resource setting. Aborting.\n");
211*4882a593Smuzhiyun return -EIO;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun pSettings->bDSPEnabled = (rSmapiInfo.bDSPEnabled && rSmapiInfo.bDSPPresent);
215*4882a593Smuzhiyun pSettings->bModemEnabled = rSmapiInfo.bModemEnabled;
216*4882a593Smuzhiyun pSettings->usDspIrq = rSmapiInfo.usDspIRQ;
217*4882a593Smuzhiyun pSettings->usDspDma = rSmapiInfo.usDspDMA;
218*4882a593Smuzhiyun pSettings->usDspBaseIO = rSmapiInfo.usDspBaseIO;
219*4882a593Smuzhiyun pSettings->usUartIrq = rSmapiInfo.usUartIRQ;
220*4882a593Smuzhiyun pSettings->usUartBaseIO = rSmapiInfo.usUartBaseIO;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun pSettings->uDStoreSize = TP_ABILITIES_DATA_SIZE;
223*4882a593Smuzhiyun pSettings->uIStoreSize = TP_ABILITIES_INST_SIZE;
224*4882a593Smuzhiyun pSettings->uIps = TP_ABILITIES_INTS_PER_SEC;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (pSettings->bDSPEnabled && pSettings->bModemEnabled && pSettings->usDspIrq == pSettings->usUartIrq) {
227*4882a593Smuzhiyun pBDData->bShareDspIrq = pBDData->bShareUartIrq = 1;
228*4882a593Smuzhiyun } else {
229*4882a593Smuzhiyun pBDData->bShareDspIrq = pBDData->bShareUartIrq = 0;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_CalcResources exit\n");
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun
tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData)238*4882a593Smuzhiyun int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun int retval = 0;
241*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
242*4882a593Smuzhiyun struct resource *pres;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
245*4882a593Smuzhiyun "tp3780i::tp3780I_ClaimResources entry pBDData %p\n", pBDData);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun pres = request_region(pSettings->usDspBaseIO, 16, "mwave_3780i");
248*4882a593Smuzhiyun if ( pres == NULL ) retval = -EIO;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun if (retval) {
251*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_ClaimResources: Error: Could not claim I/O region starting at %x\n", pSettings->usDspBaseIO);
252*4882a593Smuzhiyun retval = -EIO;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ClaimResources exit retval %x\n", retval);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun return retval;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData)260*4882a593Smuzhiyun int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun int retval = 0;
263*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
266*4882a593Smuzhiyun "tp3780i::tp3780I_ReleaseResources entry pBDData %p\n", pBDData);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun release_region(pSettings->usDspBaseIO & (~3), 16);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun if (pSettings->bInterruptClaimed) {
271*4882a593Smuzhiyun free_irq(pSettings->usDspIrq, NULL);
272*4882a593Smuzhiyun pSettings->bInterruptClaimed = false;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
276*4882a593Smuzhiyun "tp3780i::tp3780I_ReleaseResources exit retval %x\n", retval);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return retval;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun
tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData)283*4882a593Smuzhiyun int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
286*4882a593Smuzhiyun bool bDSPPoweredUp = false, bInterruptAllocated = false;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP entry pBDData %p\n", pBDData);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun if (pBDData->bDSPEnabled) {
291*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: DSP already enabled!\n");
292*4882a593Smuzhiyun goto exit_cleanup;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (!pSettings->bDSPEnabled) {
296*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780::tp3780I_EnableDSP: Error: pSettings->bDSPEnabled not set\n");
297*4882a593Smuzhiyun goto exit_cleanup;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (
301*4882a593Smuzhiyun (pSettings->usDspIrq >= s_numIrqs)
302*4882a593Smuzhiyun || (pSettings->usDspDma >= s_numDmas)
303*4882a593Smuzhiyun || (s_ausThinkpadIrqToField[pSettings->usDspIrq] == 0xFFFF)
304*4882a593Smuzhiyun || (s_ausThinkpadDmaToField[pSettings->usDspDma] == 0xFFFF)
305*4882a593Smuzhiyun ) {
306*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: invalid irq %x\n", pSettings->usDspIrq);
307*4882a593Smuzhiyun goto exit_cleanup;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (
311*4882a593Smuzhiyun ((pSettings->usDspBaseIO & 0xF00F) != 0)
312*4882a593Smuzhiyun || (pSettings->usDspBaseIO & 0x0FF0) == 0
313*4882a593Smuzhiyun ) {
314*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid DSP base I/O address %x\n", pSettings->usDspBaseIO);
315*4882a593Smuzhiyun goto exit_cleanup;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (pSettings->bModemEnabled) {
319*4882a593Smuzhiyun if (
320*4882a593Smuzhiyun pSettings->usUartIrq >= s_numIrqs
321*4882a593Smuzhiyun || s_ausThinkpadIrqToField[pSettings->usUartIrq] == 0xFFFF
322*4882a593Smuzhiyun ) {
323*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid UART IRQ %x\n", pSettings->usUartIrq);
324*4882a593Smuzhiyun goto exit_cleanup;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun switch (pSettings->usUartBaseIO) {
327*4882a593Smuzhiyun case 0x03F8:
328*4882a593Smuzhiyun case 0x02F8:
329*4882a593Smuzhiyun case 0x03E8:
330*4882a593Smuzhiyun case 0x02E8:
331*4882a593Smuzhiyun break;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun default:
334*4882a593Smuzhiyun PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Invalid UART base I/O address %x\n", pSettings->usUartBaseIO);
335*4882a593Smuzhiyun goto exit_cleanup;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun pSettings->bDspIrqActiveLow = pSettings->bDspIrqPulse = true;
340*4882a593Smuzhiyun pSettings->bUartIrqActiveLow = pSettings->bUartIrqPulse = true;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if (pBDData->bShareDspIrq) {
343*4882a593Smuzhiyun pSettings->bDspIrqActiveLow = false;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun if (pBDData->bShareUartIrq) {
346*4882a593Smuzhiyun pSettings->bUartIrqActiveLow = false;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun pSettings->usNumTransfers = TP_CFG_NumTransfers;
350*4882a593Smuzhiyun pSettings->usReRequest = TP_CFG_RerequestTimer;
351*4882a593Smuzhiyun pSettings->bEnableMEMCS16 = TP_CFG_MEMCS16;
352*4882a593Smuzhiyun pSettings->usIsaMemCmdWidth = TP_CFG_IsaMemCmdWidth;
353*4882a593Smuzhiyun pSettings->bGateIOCHRDY = TP_CFG_GateIOCHRDY;
354*4882a593Smuzhiyun pSettings->bEnablePwrMgmt = TP_CFG_EnablePwrMgmt;
355*4882a593Smuzhiyun pSettings->usHBusTimerLoadValue = TP_CFG_HBusTimerValue;
356*4882a593Smuzhiyun pSettings->bDisableLBusTimeout = TP_CFG_DisableLBusTimeout;
357*4882a593Smuzhiyun pSettings->usN_Divisor = TP_CFG_N_Divisor;
358*4882a593Smuzhiyun pSettings->usM_Multiplier = TP_CFG_M_Multiplier;
359*4882a593Smuzhiyun pSettings->bPllBypass = TP_CFG_PllBypass;
360*4882a593Smuzhiyun pSettings->usChipletEnable = TP_CFG_ChipletEnable;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun if (request_irq(pSettings->usUartIrq, &UartInterrupt, 0, "mwave_uart", NULL)) {
363*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Could not get UART IRQ %x\n", pSettings->usUartIrq);
364*4882a593Smuzhiyun goto exit_cleanup;
365*4882a593Smuzhiyun } else { /* no conflict just release */
366*4882a593Smuzhiyun free_irq(pSettings->usUartIrq, NULL);
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun if (request_irq(pSettings->usDspIrq, &DspInterrupt, 0, "mwave_3780i", NULL)) {
370*4882a593Smuzhiyun PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x\n", pSettings->usDspIrq);
371*4882a593Smuzhiyun goto exit_cleanup;
372*4882a593Smuzhiyun } else {
373*4882a593Smuzhiyun PRINTK_3(TRACE_TP3780I,
374*4882a593Smuzhiyun "tp3780i::tp3780I_EnableDSP, got interrupt %x bShareDspIrq %x\n",
375*4882a593Smuzhiyun pSettings->usDspIrq, pBDData->bShareDspIrq);
376*4882a593Smuzhiyun bInterruptAllocated = true;
377*4882a593Smuzhiyun pSettings->bInterruptClaimed = true;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun smapi_set_DSP_power_state(false);
381*4882a593Smuzhiyun if (smapi_set_DSP_power_state(true)) {
382*4882a593Smuzhiyun PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: smapi_set_DSP_power_state(true) failed\n");
383*4882a593Smuzhiyun goto exit_cleanup;
384*4882a593Smuzhiyun } else {
385*4882a593Smuzhiyun bDSPPoweredUp = true;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (dsp3780I_EnableDSP(pSettings, s_ausThinkpadIrqToField, s_ausThinkpadDmaToField)) {
389*4882a593Smuzhiyun PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: dsp7880I_EnableDSP() failed\n");
390*4882a593Smuzhiyun goto exit_cleanup;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun EnableSRAM(pBDData);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun pBDData->bDSPEnabled = true;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP exit\n");
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun return 0;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun exit_cleanup:
402*4882a593Smuzhiyun PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Cleaning up\n");
403*4882a593Smuzhiyun if (bDSPPoweredUp)
404*4882a593Smuzhiyun smapi_set_DSP_power_state(false);
405*4882a593Smuzhiyun if (bInterruptAllocated) {
406*4882a593Smuzhiyun free_irq(pSettings->usDspIrq, NULL);
407*4882a593Smuzhiyun pSettings->bInterruptClaimed = false;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun return -EIO;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun
tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData)413*4882a593Smuzhiyun int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun int retval = 0;
416*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP entry pBDData %p\n", pBDData);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (pBDData->bDSPEnabled) {
421*4882a593Smuzhiyun dsp3780I_DisableDSP(&pBDData->rDspSettings);
422*4882a593Smuzhiyun if (pSettings->bInterruptClaimed) {
423*4882a593Smuzhiyun free_irq(pSettings->usDspIrq, NULL);
424*4882a593Smuzhiyun pSettings->bInterruptClaimed = false;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun smapi_set_DSP_power_state(false);
427*4882a593Smuzhiyun pBDData->bDSPEnabled = false;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP exit retval %x\n", retval);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun return retval;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun
tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData)436*4882a593Smuzhiyun int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun int retval = 0;
439*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP entry pBDData %p\n",
442*4882a593Smuzhiyun pBDData);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (dsp3780I_Reset(pSettings) == 0) {
445*4882a593Smuzhiyun EnableSRAM(pBDData);
446*4882a593Smuzhiyun } else {
447*4882a593Smuzhiyun retval = -EIO;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP exit retval %x\n", retval);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun return retval;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun
tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData)456*4882a593Smuzhiyun int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun int retval = 0;
459*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP entry pBDData %p\n", pBDData);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun if (dsp3780I_Run(pSettings) == 0) {
464*4882a593Smuzhiyun // @BUG @TBD EnableSRAM(pBDData);
465*4882a593Smuzhiyun } else {
466*4882a593Smuzhiyun retval = -EIO;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP exit retval %x\n", retval);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun return retval;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun
tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData,MW_ABILITIES * pAbilities)475*4882a593Smuzhiyun int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun int retval = 0;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
480*4882a593Smuzhiyun "tp3780i::tp3780I_QueryAbilities entry pBDData %p\n", pBDData);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun memset(pAbilities, 0, sizeof(*pAbilities));
483*4882a593Smuzhiyun /* fill out standard constant fields */
484*4882a593Smuzhiyun pAbilities->instr_per_sec = pBDData->rDspSettings.uIps;
485*4882a593Smuzhiyun pAbilities->data_size = pBDData->rDspSettings.uDStoreSize;
486*4882a593Smuzhiyun pAbilities->inst_size = pBDData->rDspSettings.uIStoreSize;
487*4882a593Smuzhiyun pAbilities->bus_dma_bw = pBDData->rDspSettings.uDmaBandwidth;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /* fill out dynamically determined fields */
490*4882a593Smuzhiyun pAbilities->component_list[0] = 0x00010000 | MW_ADC_MASK;
491*4882a593Smuzhiyun pAbilities->component_list[1] = 0x00010000 | MW_ACI_MASK;
492*4882a593Smuzhiyun pAbilities->component_list[2] = 0x00010000 | MW_AIC1_MASK;
493*4882a593Smuzhiyun pAbilities->component_list[3] = 0x00010000 | MW_AIC2_MASK;
494*4882a593Smuzhiyun pAbilities->component_list[4] = 0x00010000 | MW_CDDAC_MASK;
495*4882a593Smuzhiyun pAbilities->component_list[5] = 0x00010000 | MW_MIDI_MASK;
496*4882a593Smuzhiyun pAbilities->component_list[6] = 0x00010000 | MW_UART_MASK;
497*4882a593Smuzhiyun pAbilities->component_count = 7;
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun /* Fill out Mwave OS and BIOS task names */
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun memcpy(pAbilities->mwave_os_name, TP_ABILITIES_MWAVEOS_NAME,
502*4882a593Smuzhiyun sizeof(TP_ABILITIES_MWAVEOS_NAME));
503*4882a593Smuzhiyun memcpy(pAbilities->bios_task_name, TP_ABILITIES_BIOSTASK_NAME,
504*4882a593Smuzhiyun sizeof(TP_ABILITIES_BIOSTASK_NAME));
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun PRINTK_1(TRACE_TP3780I,
507*4882a593Smuzhiyun "tp3780i::tp3780I_QueryAbilities exit retval=SUCCESSFUL\n");
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun return retval;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData,unsigned int uOpcode,void __user * pvBuffer,unsigned int uCount,unsigned long ulDSPAddr)512*4882a593Smuzhiyun int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
513*4882a593Smuzhiyun void __user *pvBuffer, unsigned int uCount,
514*4882a593Smuzhiyun unsigned long ulDSPAddr)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun int retval = 0;
517*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
518*4882a593Smuzhiyun unsigned short usDspBaseIO = pSettings->usDspBaseIO;
519*4882a593Smuzhiyun bool bRC = 0;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun PRINTK_6(TRACE_TP3780I,
522*4882a593Smuzhiyun "tp3780i::tp3780I_ReadWriteDspDStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n",
523*4882a593Smuzhiyun pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun if (pBDData->bDSPEnabled) {
526*4882a593Smuzhiyun switch (uOpcode) {
527*4882a593Smuzhiyun case IOCTL_MW_READ_DATA:
528*4882a593Smuzhiyun bRC = dsp3780I_ReadDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
529*4882a593Smuzhiyun break;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun case IOCTL_MW_READCLEAR_DATA:
532*4882a593Smuzhiyun bRC = dsp3780I_ReadAndClearDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
533*4882a593Smuzhiyun break;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun case IOCTL_MW_WRITE_DATA:
536*4882a593Smuzhiyun bRC = dsp3780I_WriteDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
537*4882a593Smuzhiyun break;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun retval = (bRC) ? -EIO : 0;
542*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ReadWriteDspDStore exit retval %x\n", retval);
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun return retval;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun
tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData,unsigned int uOpcode,void __user * pvBuffer,unsigned int uCount,unsigned long ulDSPAddr)548*4882a593Smuzhiyun int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
549*4882a593Smuzhiyun void __user *pvBuffer, unsigned int uCount,
550*4882a593Smuzhiyun unsigned long ulDSPAddr)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun int retval = 0;
553*4882a593Smuzhiyun DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
554*4882a593Smuzhiyun unsigned short usDspBaseIO = pSettings->usDspBaseIO;
555*4882a593Smuzhiyun bool bRC = 0;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun PRINTK_6(TRACE_TP3780I,
558*4882a593Smuzhiyun "tp3780i::tp3780I_ReadWriteDspIStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n",
559*4882a593Smuzhiyun pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun if (pBDData->bDSPEnabled) {
562*4882a593Smuzhiyun switch (uOpcode) {
563*4882a593Smuzhiyun case IOCTL_MW_READ_INST:
564*4882a593Smuzhiyun bRC = dsp3780I_ReadIStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
565*4882a593Smuzhiyun break;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun case IOCTL_MW_WRITE_INST:
568*4882a593Smuzhiyun bRC = dsp3780I_WriteIStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
569*4882a593Smuzhiyun break;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun retval = (bRC) ? -EIO : 0;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun PRINTK_2(TRACE_TP3780I,
576*4882a593Smuzhiyun "tp3780i::tp3780I_ReadWriteDspIStore exit retval %x\n", retval);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun return retval;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581