1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/char/hw_random/timeriomem-rng.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Alexander Clouter <alex@digriz.org.uk>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Derived from drivers/char/hw_random/omap-rng.c
8*4882a593Smuzhiyun * Copyright 2005 (c) MontaVista Software, Inc.
9*4882a593Smuzhiyun * Author: Deepak Saxena <dsaxena@plexity.net>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Overview:
12*4882a593Smuzhiyun * This driver is useful for platforms that have an IO range that provides
13*4882a593Smuzhiyun * periodic random data from a single IO memory address. All the platform
14*4882a593Smuzhiyun * has to do is provide the address and 'wait time' that new data becomes
15*4882a593Smuzhiyun * available.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * TODO: add support for reading sizes other than 32bits and masking
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/completion.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/hrtimer.h>
23*4882a593Smuzhiyun #include <linux/hw_random.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun #include <linux/ktime.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/of.h>
28*4882a593Smuzhiyun #include <linux/platform_device.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun #include <linux/time.h>
31*4882a593Smuzhiyun #include <linux/timeriomem-rng.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct timeriomem_rng_private {
34*4882a593Smuzhiyun void __iomem *io_base;
35*4882a593Smuzhiyun ktime_t period;
36*4882a593Smuzhiyun unsigned int present:1;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct hrtimer timer;
39*4882a593Smuzhiyun struct completion completion;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct hwrng rng_ops;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
timeriomem_rng_read(struct hwrng * hwrng,void * data,size_t max,bool wait)44*4882a593Smuzhiyun static int timeriomem_rng_read(struct hwrng *hwrng, void *data,
45*4882a593Smuzhiyun size_t max, bool wait)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct timeriomem_rng_private *priv =
48*4882a593Smuzhiyun container_of(hwrng, struct timeriomem_rng_private, rng_ops);
49*4882a593Smuzhiyun int retval = 0;
50*4882a593Smuzhiyun int period_us = ktime_to_us(priv->period);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * There may not have been enough time for new data to be generated
54*4882a593Smuzhiyun * since the last request. If the caller doesn't want to wait, let them
55*4882a593Smuzhiyun * bail out. Otherwise, wait for the completion. If the new data has
56*4882a593Smuzhiyun * already been generated, the completion should already be available.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun if (!wait && !priv->present)
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun wait_for_completion(&priv->completion);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun do {
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * After the first read, all additional reads will need to wait
66*4882a593Smuzhiyun * for the RNG to generate new data. Since the period can have
67*4882a593Smuzhiyun * a wide range of values (1us to 1s have been observed), allow
68*4882a593Smuzhiyun * for 1% tolerance in the sleep time rather than a fixed value.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun if (retval > 0)
71*4882a593Smuzhiyun usleep_range(period_us,
72*4882a593Smuzhiyun period_us + max(1, period_us / 100));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *(u32 *)data = readl(priv->io_base);
75*4882a593Smuzhiyun retval += sizeof(u32);
76*4882a593Smuzhiyun data += sizeof(u32);
77*4882a593Smuzhiyun max -= sizeof(u32);
78*4882a593Smuzhiyun } while (wait && max > sizeof(u32));
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * Block any new callers until the RNG has had time to generate new
82*4882a593Smuzhiyun * data.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun priv->present = 0;
85*4882a593Smuzhiyun reinit_completion(&priv->completion);
86*4882a593Smuzhiyun hrtimer_forward_now(&priv->timer, priv->period);
87*4882a593Smuzhiyun hrtimer_restart(&priv->timer);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return retval;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
timeriomem_rng_trigger(struct hrtimer * timer)92*4882a593Smuzhiyun static enum hrtimer_restart timeriomem_rng_trigger(struct hrtimer *timer)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct timeriomem_rng_private *priv
95*4882a593Smuzhiyun = container_of(timer, struct timeriomem_rng_private, timer);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun priv->present = 1;
98*4882a593Smuzhiyun complete(&priv->completion);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return HRTIMER_NORESTART;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
timeriomem_rng_probe(struct platform_device * pdev)103*4882a593Smuzhiyun static int timeriomem_rng_probe(struct platform_device *pdev)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct timeriomem_rng_data *pdata = pdev->dev.platform_data;
106*4882a593Smuzhiyun struct timeriomem_rng_private *priv;
107*4882a593Smuzhiyun struct resource *res;
108*4882a593Smuzhiyun int err = 0;
109*4882a593Smuzhiyun int period;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (!pdev->dev.of_node && !pdata) {
112*4882a593Smuzhiyun dev_err(&pdev->dev, "timeriomem_rng_data is missing\n");
113*4882a593Smuzhiyun return -EINVAL;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
117*4882a593Smuzhiyun if (!res)
118*4882a593Smuzhiyun return -ENXIO;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (res->start % 4 != 0 || resource_size(res) < 4) {
121*4882a593Smuzhiyun dev_err(&pdev->dev,
122*4882a593Smuzhiyun "address must be at least four bytes wide and 32-bit aligned\n");
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* Allocate memory for the device structure (and zero it) */
127*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev,
128*4882a593Smuzhiyun sizeof(struct timeriomem_rng_private), GFP_KERNEL);
129*4882a593Smuzhiyun if (!priv)
130*4882a593Smuzhiyun return -ENOMEM;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (pdev->dev.of_node) {
135*4882a593Smuzhiyun int i;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (!of_property_read_u32(pdev->dev.of_node,
138*4882a593Smuzhiyun "period", &i))
139*4882a593Smuzhiyun period = i;
140*4882a593Smuzhiyun else {
141*4882a593Smuzhiyun dev_err(&pdev->dev, "missing period\n");
142*4882a593Smuzhiyun return -EINVAL;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (!of_property_read_u32(pdev->dev.of_node,
146*4882a593Smuzhiyun "quality", &i))
147*4882a593Smuzhiyun priv->rng_ops.quality = i;
148*4882a593Smuzhiyun else
149*4882a593Smuzhiyun priv->rng_ops.quality = 0;
150*4882a593Smuzhiyun } else {
151*4882a593Smuzhiyun period = pdata->period;
152*4882a593Smuzhiyun priv->rng_ops.quality = pdata->quality;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun priv->period = ns_to_ktime(period * NSEC_PER_USEC);
156*4882a593Smuzhiyun init_completion(&priv->completion);
157*4882a593Smuzhiyun hrtimer_init(&priv->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
158*4882a593Smuzhiyun priv->timer.function = timeriomem_rng_trigger;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun priv->rng_ops.name = dev_name(&pdev->dev);
161*4882a593Smuzhiyun priv->rng_ops.read = timeriomem_rng_read;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun priv->io_base = devm_ioremap_resource(&pdev->dev, res);
164*4882a593Smuzhiyun if (IS_ERR(priv->io_base)) {
165*4882a593Smuzhiyun return PTR_ERR(priv->io_base);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Assume random data is already available. */
169*4882a593Smuzhiyun priv->present = 1;
170*4882a593Smuzhiyun complete(&priv->completion);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun err = hwrng_register(&priv->rng_ops);
173*4882a593Smuzhiyun if (err) {
174*4882a593Smuzhiyun dev_err(&pdev->dev, "problem registering\n");
175*4882a593Smuzhiyun return err;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun dev_info(&pdev->dev, "32bits from 0x%p @ %dus\n",
179*4882a593Smuzhiyun priv->io_base, period);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
timeriomem_rng_remove(struct platform_device * pdev)184*4882a593Smuzhiyun static int timeriomem_rng_remove(struct platform_device *pdev)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct timeriomem_rng_private *priv = platform_get_drvdata(pdev);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun hwrng_unregister(&priv->rng_ops);
189*4882a593Smuzhiyun hrtimer_cancel(&priv->timer);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return 0;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct of_device_id timeriomem_rng_match[] = {
195*4882a593Smuzhiyun { .compatible = "timeriomem_rng" },
196*4882a593Smuzhiyun {},
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, timeriomem_rng_match);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static struct platform_driver timeriomem_rng_driver = {
201*4882a593Smuzhiyun .driver = {
202*4882a593Smuzhiyun .name = "timeriomem_rng",
203*4882a593Smuzhiyun .of_match_table = timeriomem_rng_match,
204*4882a593Smuzhiyun },
205*4882a593Smuzhiyun .probe = timeriomem_rng_probe,
206*4882a593Smuzhiyun .remove = timeriomem_rng_remove,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun module_platform_driver(timeriomem_rng_driver);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun MODULE_LICENSE("GPL");
212*4882a593Smuzhiyun MODULE_AUTHOR("Alexander Clouter <alex@digriz.org.uk>");
213*4882a593Smuzhiyun MODULE_DESCRIPTION("Timer IOMEM H/W RNG driver");
214